Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Core Architecture
Lucent Technologies Inc.
DRAFT COPY
5-11
5.2 X Address Arithmetic Unit (XAAU)
The X address arithmetic unit (XAAU) is shown in Figure 5-5 . It consists of a 16-bit adder; an offset register (i); and
four pointer registers: the program counter (PC
1
), the program return (pr), the program interrupt (pi), and the table
pointer (pt). These registers are used to address the X space memory or instruction/coefficient memory. The i
register is used to postmodify the pt register. The pt, pr, pi, and i registers are user-accessible and can be modi-
fied under program control. All of the registers are 16 bits wide. All contain unsigned data except for i which con-
tains signed data. The X-memory space contains internal ROM, the internal dual-port RAM, and external
memory. The X-memory space is described in
Section 3.2, Memory Space and Addressing .
5-4158
Figure 5-5. XAAU—X Address Arithmetic Unit
5.2.1 Inputs and Outputs
The outputs of the XAAU are the instruction/coefficient address bus XAB and the memory segment enables (see
Section 5.2.2, X-Memory Space Segment Selection ). The internal data bus IDB provides access to all of the regis-
ters except PC.
5.2.2 X-Memory Space Segment Selection
The 64K addresses in the X-memory space are divided into three segments: ROM, RAM, and EROM (see Section
3.2, Memory Space and Addressing ). These three segments can be arranged four different ways (four different
memory maps) in the space. The XAAU provides enable lines for the three segments. Additionally, the RAM seg-
ment is divided into multiple banks of 1 Kwords each. Each bank has an enable line from the XAAU. The enable
lines are enabled one at a time depending on the address and the memory map.
1.The upper case denotes that this register is not accessible by instructions.
i (16)
1
MUX
ADDER
PC (16)
pt (16)
pi (16)
16
ADDRESS
BUS
16
XAAU
(16)
pr(16)
XAB
IDB
MEMORY
SEGMENT
ENABLES