Lucent Technologies DSP1611, Information Manual, Page: 119 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set April 1998
4-2
DRAFT COPY
Lucent Technologies Inc.
4.1 Notation
These operators are used to describe the instruction set:
For all instructions listed in this chapter, the following are true:
Brackets, [ ], are not part of the instruction syntax but indicate that the enclosed item is optional.
Parentheses, ( ), and braces, { }, are part of the instruction syntax and must appear where shown in the instruc-
tion.
Arrow brackets, < >, are not part of the instruction syntax but indicate that one of the enclosed items or a proper
statement must be included to form a valid instruction.
Upper-case characters in instructions denote a replacement character that is to be replaced by a specific value.
For example, consider the pointer register rM, where M is replaced by 0, 1, 2, or 3.
F Titles
F1, F2, F3, and F4 are terms used to differentiate classes of instructions or statements.
They are defined as follows:
F1: Multiply/ALU operator statements
F2: Operator statements for special function instructions (if CON F2)
F3: ALU instructions
F4: BMU instructions
The valid instruction groups for the DSP device are represented in Tables 4-1 to 4-17 . The items in these tables
that are written in lower-case letters are proper statements and must appear where shown in the instruction. The
items with capital letters are not proper statements and are replaced with immediate data, a register name, or a
condition. For example, aD would be either a0 or a1. The valid replacement values for upper-case items are listed
in the replacement tables.
4.2 Instruction Cycle Timing
For the DSP1611/17/18/27/28/29, the instruction cycle is defined as the execution time of a single-cycle instruction
in the absence of wait-states. For a 60 MHz 2x CKI or a 30 MHz 1x CKI, the instruction cycle is 33 ns. For the
Operator Meaning
* 16 x 16 32-bit multiplication
(Denotes register-indirect addressing if used as a prefix to an address register.)
+ 36-bit addition
†
† The ALU performs 36-bit operations, but the operands can be 16, 32, or 36 bits.
– 36-bit subtraction
†
++ Register postincrement
–– Register postdecrement
>> Arithmetic right shift
<< Arithmetic left shift
>>> Logical right shift
<<< Logical left shift
& 36-bit bitwise AND
†
| 36-bit bitwise OR
†
^ 36-bit bitwise EXCLUSIVE OR
†
: Compound addressing
~ One's complement