Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Lucent Technologies Inc.
DRAFT COPY
4-1
4 Instruction Set
All DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 instructions are 16 bits wide and resemble
C code. The instructions are grouped into seven categories:
Control instructions direct program flow and can be conditionally executed on the basis of the state of internal
flags.
Cache instructions implement low-overhead loops by loading a set of instructions into a cache memory and
repetitively executing them (up to 127 times).
Data move instructions transfer data between registers, memory, and accumulators. Immediate loads of regis-
ters and accumulators are also possible.
Special function instructions perform accumulator operations such as incrementing, rounding, negation, logical
left shifts, and arithmetic right shifts. Special function instructions also permit a single-cycle 32-bit load of an
accumulator from either the p or y register. These special function instructions can be conditionally executed on
the basis of the state of internal flags.
Multiply/ALU instructions are the primary instructions for signal-processing programs that perform multiply/accu-
mulate, logical, and other ALU functions. They also transfer data between memory and registers in the data arith-
metic unit. Flags are set based on accumulator results.
ALU instructions perform operations between two accumulators, between an accumulator and the product regis-
ter, or between an accumulator and an immediate data word. The operations are add, subtract, AND, OR, and
exclusive OR. Flags are set based on accumulator results.
BMU instructions perform full barrel shifting, extraction of an exponent, normalization, and extraction or insertion
of an arbitrary field of bits on the accumulators. An instruction shuffles data between the accumulators and one
of the alternate accumulators. Flags are set based on results.
Note: The only instruction groups that set flags are the multiply/ALU, special function, ALU, and BMU groups.
Also, certain flags are set by the BIO.
The following sections describe the notation, the instruction cycle timing, the addressing modes, the internal flags
used by conditional instructions, and the seven groups of instructions. Appendix B describes each instruction indi-
vidually.
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...