Lucent Technologies DSP1611, Information Manual, Page: 93 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998
3-40
DRAFT COPY
Lucent Technologies Inc.
3.4 Interrupts
(continued)
3.4.6 Powerdown with the AWAIT State
These DSPs have a power-saving standby mode in which the internal clock is stretched indefinitely until an inter-
rupt/trap request is received. A minimum amount of circuitry on the chip, including the PIO/PHIF and SIO, will con-
tinue to run in order to process the incoming interrupt. The processor enters the powerdown mode by the user
setting the AWAIT bit (bit 15) of the alf register. After the AWAIT bit is set, one more instruction cycle is executed
before entering the standby powerdown mode. After an interrupt request wakes up the processor, one more
instruction cycle is executed before being interrupted. The timing of entering and exiting the sleep mode is illus-
trated in
Figure 3-15 .
5-4120
† CKO is a free-running clock (ioc = 0x0000).
‡ CKO is a wait-stated clock (ioc = 0x0080).
Notes:
A. Setting AWAIT bit of the alf register.
B. Executing one more instruction (nop) after AWAIT is set.
C. Stretching the clock for powerdown mode.
D. Executing one more instruction (nop) after coming out of sleep mode.
E. Branching to interrupt service routine.
F. Start executing instructions in interrupt service routine.
Figure 3-15. Timing Diagram of Entering and Exiting Powerdown Mode
CKO
‡
IACK
VEC[3:0]
A B C
D E F
INT1
CKO
†