BAT32G1x9 user manual | Chapter 10 Timer M
406 / 1149
Rev.1.02
register and the PWM waveform is output when the TM1 counter underflow occurs. After the PWM
waveform is output, the value of the buffer register is transmitted to the general-purpose register via
the timing set by CMD0 bits.
However, the output of 100% positive phase and 0% duty cycle of inverting phase cannot be set with
the initial value of the buffer register "FFFFH". Nor can it be directly changed from the output of 100%
positive phase duty cycle and inverting 0% duty cycle to the output of positive phase 0% duty cycle
and inverting phase 100% duty cycle.
The case where the value of the buffer register is "0000H" (100% duty cycle) data transfer occurs
when the TM0 and TMGRA0 registers are relatively matched.
Thereafter, if you set a value for th
e buffer register (0001H≤ set the value <TMGRA0Register value),
just after settingTM0
和
TMGRA0Register occurrence1When the second comparison matches, the
data is transferred to a general purpose register. Then, passCMD0Bit sumCMD1The bit selects the
time series for data transfer.
Figure 10-67 Example of operation when the buffer register in complementary PWM mode has a value of
"0000H"
TM0 register
counting value
TMGRD0
register
TMGRB0
register
TMIOB0 output
TMIOD0 output
when content of
TMGRD0 register is
0000H, thus when
TM0 and TMGRA0
compare matching,
data is transmitted.
after that, when
0001H
n1<m for
the very first time,
thus when TM0
and TMGRA0
compare
matching, data is
transmitted.
TM 0 c o un t e r
v a lu e
TM 1 c o un t e r
v a lu e
configure timing sequence to perform
data transmission via CMD0 bit and
CMD1 bit.
configure timing sequence to
perform data transmission via
CMD0 bit and CMD1 bit.
transmit
transmit
transmit
transmit
Time
If you write "0000H" to the buffer register, the value of the buffer register is passed to the general-
purpose register when the TM0 register and the TMGRA0 registers are relatively matched, and fixed
to a positive phase 0% duty cycle and an inverting 100 % The output level of the duty cycle,
independent of the setting of the CMD0 bit.
To desertin
g the output level, the buffer register must be set (the value of the TM0 register≤ the value
of the ≤ (the value of the TMGRA0 – the value of the TM0 register)). After writing the buffer, regardless
of the setting of the CMD0 bit, the value of the buffer register is transferred to the general-purpose
register and the PWM waveform is output when the TM1 counter underflow occurs. After the PWM