BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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Rev.1.02
Table 20-4
Status at the time of arbitration and timing of generation of interrupt requests
The state in which the arbitration occurred
Timing of the generation of interrupt requests
Address during sending
The descending edge of the 8th or 9th clock after the byte
transfer is
note 1
Read and write information after sending the address
The extension code is being sent during process
Read and write messages after sending extension codes
During data sending
After sending the data, the reply is delivered during the
transfer
A restart condition was detected during data transfer.
A stop condition was detected during data transfer.
Note 2
when generating a stop condition (SPIEn=1).
You want to generate a restart condition, but the data is
low.
The descending edge of the 8th or 9th clock after the byte
transfer is
note 1
You want to build a restart condition, but a stop condition is
detected.
Note 2
when generating a stop condition (SPIEn=1).
You want to generate a stop condition, but the data is low. The descending edge of the 8th or 9th clock after the byte
transfer is
note 1
You want to generate a restart condition, but SCLAn
is low.
Note: 1
When
the WTIMn
bit (bit3
of
the IICA
control register
n0
(IICCTLn0))
is
"1", in the The
falling edge of the 9 clocks
generates an interrupt request; When
the WTIMn
bit is
"0"
and a slave address of the extension code is received,
an
interrupt request is generated on the descending edge of the 8th clock.
2. When there is a possibility of arbitration,
the SPIEn
position
must be "1"
when the master is running
.
Note: 1. SPIEn:
bit4
of
the IICA
control register
n0
(IICCTLn0
).
2.n=0,1
