Cmsemicon BAT32G1 9 Series, User Manual

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BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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3. To undo the wait during the slave send, the data must be
written to
the IICAn instead of the WRELn position bit.
FIG 20-31 of the "(1) start condition ~ address ~ data" of (1) ~ (7) description is as follows:
①
If the master sets the start condition trigger set (STTn=1), the bus data line (SDAAn) drops and the
start condition is generated (SDAAn is changed from "1" to "0" by SCLAn=1). )
。
Thereafter, if a
start condition is detected, the master enters the master communication state ( MSTSn=1) and
after the hold time elapses the bus clock line drops ( SCLAn=0,1), ending the communication
preparation.
②
If the master writes aR (receive) to the IICA shift register n (IICAn), the slave address is
sent.
③
On the slave, if the receiving address and the local station address (the value of the SVAn) are the
same note, an ACK is sent to the master through hardware. The master detects ACK on the rising
edge of the 9th clock (ACKDn=1).
④
The master generates an interrupt on the falling edge of the 9th clock (INTIICAn: address send end
interrupt). Slaves with the same address enter a waiting state (SCLAn=0,1) and an interrupt
(INTIICAn: address matching interrupt)
note
.
⑤
The master changes the wait sequence to the 8th clock (WTIMn=0,1).
⑥
The slave writes and sends data to the IICAn register, relieving the slave of the wait.
⑦
The master relieshes the wait (WRELn=1) and begins data transfer from the slave.
Note: If the sent address and the slave address are different, the slave does not return an ACK (NACK: SDAAn=1
)
to the master
, and does not generate an INTIICAn interrupt (address matching interrupt) or enter a waiting state.
However, the master generates ANTIICAn interrupts
(address send end interrupts) for
both
ACK
and NAK.
Note 1
FIG 20-31
(19)
A series of operating steps for data communication via
the I2C bus.
FIG 20-31
of the "(1) start condition ~ address ~ data" illustrates steps (1) ~ (7).
FIG 20-31
of the "(2) address ~ data ~ data" illustrates steps (3) ~ (12).
FIG 20-31
of the "(3) data ~ data ~ stop condition" illustrates steps (8) ~ (19).
2.n=0,1