BAT32G1x9 user manual | Chapter 4 Clock generation circuit
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Rev.1.02
4.3.3
Clock Operating State Control Register (CSC).
This is the register that controls the operation of the high-speed system clock, the high-speed internal
oscillator clock, and the sub-system clock (except for the low-speed internal oscillator clock). Set the CSC
registers via the 8-bit memory operation instructions.
After a reset signal is generated, the value of this register changes
to "C0H".
Figure 4-4
Clock Operating State Control Register (CSC).
Address: 40020401H
reset:
C0H R/W
symbol
CSC
MSTOP
Operational control of high-speed system clocks
X1 oscillation mode
External clock input
mode
Enter the port mode
0
The X1 oscillation circuit
operates
The external clock on the
EXCLK pin is valid
Enter the port
1
The X1 oscillation circuit stops
The external clock on the
EXCLK pin is invalid
XTSTOP
Operational control of the sub-system clock
XT1 oscillation mode
External clock input
mode
Enter the port mode
0
The XT1 oscillation circuit
operates
The external clock on the
EXCLKS pin is valid
Enter the port
1
The XT1 oscillation circuit
stops
The external clock of the
EXCLKS pin is invalid
HIOSTOP
Operational control of the high-speed internal oscillator clock
0
High-speed internal oscillator operation
1
High-speed internal shaker stop
Note 1
After the reset is released, the CSC register must be set after the clock operating mode control register (CMC) is
set.
2. After reset released and before placing the MSTOP position "0", the Oscillation Settling Time Selection Register
(OSTS) must be set. However, when using the OSTS register at the initial value, there is no need to set the OSTS
register.
3. To start the oscillation of X1 by setting the MSTOP bit, the oscillation settling time of the X1 clock must be
confirmed by the state register (OSTC) of the oscillation settling time counter.
4. To start XT1 oscillation by setting the XSTOP bit, it is necessary to wait through the software for the desired
oscillation stabilization time of the subsystem clock.
5. The clock that is selected as the CPU/Peripheral Hardware Clock (f
CLK
) cannot be stopped through the CSC
registers.
6. Refer to Table Table 4-2).
Table 4-2
Clock Stop Method
clock
Condition before clock stop (external clock input is
invalid)
Flag setting for CSC
registers
X1 clock
The CPU/peripheral hardware clock runs on a clock other than the
high-speed system clock.
(CLS=0
and
MCS=0, or
CLS=1).
MSTOP=1
External master system
clock
XT1 clock
The CPU/peripheral hardware clock runs on a clock other than the
secondary system clock.
(CLS=0)
XTSTOP=1
External subsystem
clock
High-speed internal
oscillator clock
The CPU/peripheral hardware clock runs at a clock other than the
high-speed internal oscillator clock.
(CLS=0
and
MCS=1, or
CLS=1).
HIOSTOP=1
7
6
5 4 3 2 1
0
MSTOn
XTSTOn
0
0
0
0
0
HIOSTOn