BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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Rev.1.02
6.2.2
Timer count register mn (TCRmn).
The TCRmn register is a 16-bit read-only register that counts the counting clock. Increments or decrements
synchronously with the rising edge of the counting clock.
The operating mode is selected by the MDmn3 to MDmn0 bits of the timer mode register mn (TMRmn), and
the increment and decrement counts are switched (see "6.3.3 Timer Mode Registers"). mn (TMRmn)
”) .
Figure 6-2
Timer count register mn (TCRmn).
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1
0
TCRmn
Note: m: unit number (m=0,1) n: channel number (when m=0: n=0~3, m=1: n=0~7).
The count value can be read by reading the timer count register mn (TCRmn).
In the following cases, the count value becomes "FFFFH".
•
When a reset signal is generated
•
When clearing
the TM4EN/TM8EN bit of peripheral enable register 0 (PER0).
•
End of count of dependent channels in PWM output mode
•
The count of dependent channels ends in delay counting mode
•
At the end of the count of the master/slave channel in single trigger pulse output mode
•
End of count of dependent channels in multiple PWM output mode
In the following cases, the count value becomes "0000H".
•
Enter when the trigger starts in capture mode
•
Capture at the end in capture mode
Note: Even if the TCRmn
register is read, the count value is not captured to the timer data register mn
(TDRmn).
