BAT32G1x9 user manual | Chapter 23 LCD bus interface
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23.4 Runtime order
This section describes the timing of general operations, and then describes examples of sequential write
and read operations.
23.4.1
Timing relationships
The following figure shows the general timing when using the 80 pattern. It illustrates the effect of LBCYC
and LBWST register settings. The impact of LBCTL.TCIS on INTLCDB is also explained.
Figure23-8
LCD
bus interface timing
(mode 80).
In mode 80, D B W R
————————
is the optional communication number for the write action, D B R D
———————
is the optional
communication number for the read action
Note: 1
T
is the clock
cycle of the internal clock
SPCLK
(configured by
LBC1
and
LBC0 bits).
2. CYC is the number of clock cycles selected by LBCYC. LBCYC >2 is required.
3. WST is the number of wait state clock cycles selected by LBWST and requires LBWST < (LBCYC
–2).
The 68 mode and 80 mode signals have different meanings: DBWR is replaced with the read-write select
communication number R/W
——
, and DBRD is replaced with the strobe enable signal E, which selects the
communication number The effective level of E is determined by LBCTL.EL.
