BAT32G1x9 user manual | Chapter 10 Timer M
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Rev.1.02
•The data transfer timing from the buffer register to the general-purpose register must be selected by the
CMD0 bit and CMD1 bit of the TMFCR register. However, in the case of 0% duty cycle and 100%
duty cycle, regardless of the values of CMD0 bits and CMD1 bits, the following transmission timing
is the following.
The value of the buffer register ≥ the value of the TMGRA0 register (0% duty cycle) data transfer
occurs when the TM1 register underflow occurs.
Thereafter, if you set a value for the buffer register (
0001H≤ set the value <TMGRA0Register value),
just after settingTM1Register occurrence1Transmits data to a general purpose register on the second
underflow. Then, passCMD0Bit sumCMD1The bit selects the time series for data transfer.
However, a waveform with a 0% duty cycle cannot be generated when the initial value of the buffer
register is "FFFFH". To generate a waveform with a 0% duty cycle, the value of the buffer register
must be ≥ the value of the TMGRA0 register by writing the buffer register.
Figure 10-66 Example of operation when the value of the buf
fer register in the complementary PWM mode ≥ the
value of the TMGRA0 register
TM0 register counting value
TMGRD0 register
TMGRB0 register
TMIOB0 output
TMIOD0 output
TM 1
TM 1
TM 0 c o un t e r
v a lu e
TM 1 c o un t e r
v a lu e
configure timing sequence to
perform data transmission via
CMD0 bit and CMD1 bit.
while n3>m, thus
when TM1 register
underflows, data is
transmitted.
after that, when
n2<m for the very
first time, thus
when TM1 register
underflows, data is
transmitted.
configure timing sequence to perform
data transmission via CMD0 bit and
CMD1 bit.
transmit
transmit
transmit
transmit
Time
If you set a value for the buffer register (the setting value ≥ the value of the TMGRA0 register), the
value of the buffer register is passed to the general purpose register just when the TM1 counter
underflows, and it is fixed to the output level of 100% positive phase duty cycle and inverting 0% duty
cycle The setting of cmD0 bits is independent.
To desetting the output level, the buffer register mus
t be set (the value of the TM0 register≤ the value
of the ≤ (the value of the TMGRA0 – the value of the TM0 register)). After writing the buffer, regardless
of the setting of the CMD0 bit, the value of the buffer register is transferred to the general-purpose
