Cmsemicon BAT32G1 9 Series, User Manual, Page: 174 / 1149

BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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6.5.3 The operation of the counter
The counter operation for each mode is described below.
(1) Operation of interval timer mode
(1) By writing "1" to the TSmn bit, enter the run Enabled state (TEmn=1). The timer count register mn
(TCRmn) remains at its initial value until a count clock is generated.
(2) Generate a start trigger signal by allowing the first counting clock (fMCK) after running.
(3) When the MDmn0 bit is "1", the INTMmn is generated by starting the trigger signal.
(4) Load the value of the timer data register mn (TDRmn) into the TCRmn register by allowing the first
counting clock after running, and start counting in interval timer mode.
(5) If the TCRmn register is decremented to "0000H", the INTMmn is generated by the next count clock
(fMCK), and the timer data register mn is generated The value of (TDRmn) continues counting after
loading into the TCRmn register.
Figure 6-26 Runtime Sequence (Interval Timer Mode).
when MDmn0 = 1
INTTMmn
TDRmn
TCRmn
start trigger
detection
singal
TEmn
TSmn(write)
f
MCK
(f
TCLK
)
initial value m m-1
0001 0000
m
m
Note: Because the first count clock cycle runs after the TSmn bit is written and the start of the count is delayed before
the count clock is generated, an error of up to 1 clock cycle is generated. In addition, if information about starting
counting timing is required, the MDmn0 position is "1" so that an interrupt can be generated at the start of
counting.