BAT32G1x9 user manual | Chapter 13 Clock output/buzzer output control circuitry
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Rev.1.02
13.4 the operation of Clock output/buzzer output controls circuitry
It can be selected as a clock output or buzzer output with 1 pin.
The CLKBUZ0 pin outputs a clock/buzzer selected by clock output select register 0 (CKS0).
The CLKBUZ1 pin outputs a clock/buzzer selected by clock output select register 1 (CKS1).
13.4.1
Operation of the output pins
The CLKBUZn pin is output as follows:
①
The position "0" of the port mode register (PMxx) and the port register (Pxx) that will be used as
the port of the CLKBUZ0 pin.
②
Select bit0 to 3 (CCSn0 ~CCSn2), register select register (CKSn) through the clock output of
the CLKBUZn pin CSELn) selects the output frequency (output is disabled).
③
Place bit7 (PCLOEn) of the CKSn register at "1" to allow the output of the clock/buzzer.
Note 1
When used as a clock output, the control circuit starts or stops the clock output
after
allowing
or
disabling one clock after the clock output (
PCLOEn
bit). Pulses with narrow widths are not output at
this time. The
timing of the outputs allowed or stopped by the PCLOEn bits and the timing of the clock
outputs is
shown in Figure
13-3.
2. n=0, 1
Figure 13-3 clock output timing of the
CLKBUZn pin
after 1 clock cycle
clock output
narrow pulses not recognized
13.5 Considerations for clock output/buzzer output control circuitry
When the main system clock is selected as the CLKBUZn output (CSELn=0), if 1.5 after the stop output
(PCLOEn=0) is set
The output clock of the CLKBUZn pin is shifted to deep sleep mode, and the output width of CLKBUZn is narrowed.
