BAT32G1x9 user manual | Chapter 19 Universal serial communication unit
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Rev.1.02
19.2.1
Shift Register (SCI0)
This is a 9-bit register that converts parallel and serial to and from each other.
For UART communication at 9 bits of data length, use 9 bits (bit0 to 8)
Note
1
。
Convert the input data of
the serial input pins into parallel data when receiving data; When data is sent, the value that will be
transferred to this register is output as serial data from the serial output pin
note
1
. Shift registers cannot be
manipulated directly through the program.
To read and write data from the shift register, use the low 8 bits or 9 bits low of the serial data register
mn (SDRmn).
19.2.2
The serial data register mn (SDRmn) is either 8 bits low or 9 bits low (SCI0).
The SDRmn register is the transmit and receive data registers (16 bits) of channel n.
Bit8~0 (low 9 bits)
note
or bit7~0 (low 8 bits) is used as transmit and receive buffer registers Bit15~9 is
used as a crossover setting register for the operating clock (f
MCK
).
When receiving data, save parallel data converted by shift registers to a low 8 bit or a low 9 bit; When
sending data, the transmit data transmitted to the shift register is set to 8 bits low or 9 bits low.
Regardless of the output order of the data, bit0 and bit1 (DLSmn0, DLSmn1) of the set register mn
(SCRmn) are run according to serial communication ) settings, save to the low 8 bits or low 9 bits data as
follows:
• 7 bits of data length (bit0~6 saved in the SDRmn register).
• 8 bits of data length (bit0~7 saved in the SDRmn register).
• 9 bits of data length (bit0~8 saved in the SDRmn register)
Note
1
SDRmn registers can be read and written in 16-bit increments.
Depending on the communication mode, the lower 8 bits of the SDRmn register or the low 9 bits of the
SDRmn register can be read and written in 8 bits by the following SFR name.
•
SSPIp communication... SDIOp (SSPIp Data Register).
•
UARTq receives... RXDq (UARTq Receive Data Register).
•
UARTq sends... TXDq (UARTq Transmit Data Register).
•
IICr communication... SDIOr (IICr Data Register).
After generating the reset signal, the value of the SDRmn register changes to "0000H".
Note 1
Only
UART0
supports
9
bits of data length.
2. When the operation stops (SEmn=0), it is forbidden to
rewrite
SDRmn [7:0] through the
8-bit memory operation
instruction
(otherwise,
SDRmn [15:9]
is all cleared
"0").
Note 1
At the end of the reception, bits
from
bit0
to
8
that exceed the length of the data are
bits "0".
2.m: unit number (m=0) n: channel number (n=0, 1) p: SSPI number (p=00, 01, 10, 11)
q: UART number (q=0, 1) r: IIC number (r=00, 01, 10, 11)
8
7
6
5
4
3
2
1
0
Shift register
