BAT32G1x9 user manual | Chapter 10 Timer M
376 / 1149
Rev.1.02
(1) Operation example
By setting the CCLR0 to CCLR2 bits of the TMCRi registers (i=0, 1), the timer M i is applied when input
capture or comparison matching occurs The count value is reset. Fig. 10-47 is an example of the operation
when the CCLR2~CCLR0 position "001B" is used. If it is set to count clearing by input capture during operation
and input capture when the timer's count value is "FFFFH", the IMFA~IMFD of the TMSRi register depends on
the runtime sequence of the counting source and input capture The interrupt flag for both bits and OVF bits
may change to "1" at the same time.
Figure 10-47
An example of an input capture function
TMCLK input
counting source
TMi register
counting value
FFFFH
0009H
0006H
0000H
time
TSTARTi bit of
TMSTR register
65536
TMDIOAi input
0006H
0009H
TMGRAi
register
0006H
TMGRCi
register
IMFA bit of
TMSRi register
OVF bit of
TMSRi register
transmit
transmit
set to 0 via program
Note i=0
，
1
above diagram condition as following:
CCLR2~CCLR0 bit of TMCRi register as "001B" (set Tmi bit as "0000H" while TMGRAi input capture)
TCLK2~TCLK0 bit of TMCRi register as "101B" (Counting source as TMCLK input)
CKEG1 bit and CKEG0 bit of TMCRi register as "01B" (counting at falling edge of counting source).
IOA2~IOA0 bit of TMIORAi register as "101B" (input capture at falling edge of TMIOAi input)
TMBFCi bit of TMMR register as "1" (TMGRCi register is the buffer register of TMGRAi register)
