Cmsemicon BAT32G1 9 Series, User Manual, Page: 961 / 1149

BAT32G1x9 user manual | Chapter 22 CAN control
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961 / 1149 Rev.1.02
Clear VALID bit
Clear the RDY bit
Begin
no
t
RDY=1?
yes
RDY=0?
no
t
yes
RSTAT=0Or
InALID=1?
Note1
no
t
end
Fig.22-64shows the receive packet cache processing (CnMCONFm register MT[2:0] bits = 001B to 101B).
Fig.22-64. Packet cache redefinition
yes
Note2
Wait for 4 CAN data bits
Set up
message
caching
Set the RDY bit
Note 1. Acknowledgement of receipt of the message is due to the fact that the message has been fully
receivedRDYBits are set.
2. Avoid redefining the packet buffer during a stored packet receive operation by waiting for an
additional 4 CAN data bits.