BAT32G1x9 user manual | Chapter 10 Timer M
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Rev.1.02
Table 10-14 Specifications for PWM functions
project
specification
Count the sources
f
CLK
, f
CLK
/2, f
CLK
/4, f
CLK
/8, f
CLK
/32
An external input signal from the TMCLK pin that can
programmatically select valid edges
count
Increment the count
PWM waveform
PWM period:
1/fk
(m+1)
Effective level width:
1/fk
(m
–n)
Invalid level width:
1/fk
(n+1).
fk: The frequency at which the source is counted
m: The setting value of the TMGRAi register
n: The setting value of the TMGRji register
m+1
n+1m
–n (when the effective level is "L").
Count start criteria
Write "1" (start counting) to the TSTARTi bit of the TMSTR register.
Count stop conditions
• Write "0" (stop count) to the TSTARTi bit when the CSELi bit of the TMSTR register is "1".
The PWM output pin holds the output level before stopping the count.
• Stop counting when the CSELi bit of the TMSTR register is "0" and a comparison match of
TMGRAi occurs.
The PWM output pins remain relatively matched after the output changes.
Timing of the generation of
interrupt requests
• Comparison matching (TMi registers and TMGRhi registers have the same content).
• Overflow of TMi
TMIOA0 pin function
I/O port or TMCLK (external clock) input
TMIOA1 pin function
I/O port
TMIOB0,
TMIOC0,
TMIOD0,
TMIOB1,
TMIOC1, TMIOD1
Pin function
I/O port or PWM output (select by pin).
INTP0 pin function
The pulse output is the input of the forced cutoff signal (input dedicated port or INTP0
interrupt input).
Read timer
If you read the TMi
register, you can read the count value.
Write timer
Can write TMi
registers.
Select Features
• Selection of 1 to 3 PWM output pins via timer Mi
One or more pins in the TMIOBi, TMIOCi, TMIODi pins
• Selection of effective levels for each pin
• Selection of initial output levels for each pin
•Synchronous run (see "10.4.3 sync run").
•Buffer run (see "10.4.2 buffer run").
•Input of the pulse output forced cutoff signal (see "Forced cutoff of 10.4.4 pulse output").
Remark
i=0, 1,j=B, C, D,h=A, B, C, D