BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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Rev.1.02
Note: 1 To lift the wait, the IICAn must be placed in the "FFH" position or the WRELn position
must be placed.
2. After the release of the stop condition, the time from the SCLAn pin signal to generate the stop
condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
3. To undo the wait during the slave send, the data must be written to the IICAn instead of the WRELn
position bit.
4. During the sending of the slave, if the wait is lifted by the assertion of the WRELn bit, the TRCn bit is
cleared.
FIG 20-31 of "(3) data ~ data ~ stop condition" of (8) ~ (19) description is as follows:
⑧
.
The master enters a waiting state (SCLAn = 0,1) on the falling edge of the 8th clock and
generates an interrupt (INTIICAn: Transmit End-of-Off). Because the ACKEn bit of the master is
"0", the ACK is sent to the slave through the hardware.
⑨
.
The master reads the received data and dismisses the wait (WRELn=1).
⑩
.
The slave detects ACK (ACKDn=1) on the rising edge of the 9th clock.
⑪
.
The slave enters a waiting state on the falling edge of the 9th clock (SCLAn= 0,1) and generates
an interrupt (INTIICAn: transmit end interrupt).
⑫
.
If the slave writes and transmits data to the IICA shift register n (IICAn), the slave's wait is lifted
and the transfer of data from the slave to the master begins.
⑬
.
The master generates an interrupt (INTIICAn: transmit end interrupt) on the falling edge of the 8th
clock and enters a waiting state (SCLAn=0,1). Because ACK control (ACKEn=1) occurs, the bus
data line at this stage becomes low (SDAAn=0,1).
⑭
.
The master sets the NACK Acknolwdge (ACKEn=0,1) and changes the wait sequence to the 9th
clock (WTIMn=1). If the master relieshes the wait (WRELn=1), the slave detects THEACK
(ACKDn=0,1) on the rising edge of the 9th clock.
⑮
.
Both the master and slave enter a waiting state (SCLAn=0,1) on the falling edge of the 9th clock,
and both produce an interrupt (INTIICAn: end-of-transmit interrupt).
⑯
.
If the master issues a stop condition (SPTn=1), the bus data cable (SDAAn=0,1) is cleared and
the master's wait is lifted. After that, the master is on standby until the bus clock line is set in place
(SCLAn=1).
⑰
.
The slave stops sending after confirming the NAK, in order to end the communication, the wait is
lifted (WRELn=1). If the slave wait is lifted, the bus clock line is set in place (SCLAn=1).
⑱
.
If the master confirms that the bus clock line is set (SCLAn=1), the bus data line is set after the
stop condition preparation time has elapsed
⑲
.
(SDAAn=1), and then issue a stop condition (SDAAn is changed from "0" to "1" by SCLAn=1). If a
stop condition is generated, the slave detects the stop condition and generates an interrupt
(INTIICAn: Stop Condition Interrupt).
