BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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Rev.1.02
(3) Operation of capture mode (interval measurement of input pulses).
(1) By writing "1" to the TSmn bit, enter the run Enabled state (TEmn=1).
(2) The timer count register mn (TCRmn) maintains the initial value until the count clock is generated.
(3) Generate a start trigger signal by allowing the first counting clock (fMCK) after running. Then, load
"0000H" into the TCRmn register and start counting in capture mode (when MDmn0 bit is "1", intTMmn is
generated by starting the trigger signal)
。
(4) If a valid edge of the TImn input is detected, the value of the TCRmn register is captured to the TDRmn
register and an INTTmn interrupt is generated. The captureped value at this point is meaningless. The
TCRmn register continues counting starting at "0000H".
(5) If a valid edge of the next TImn input is detected, the value of the TCRmn register is captured to the
TDRmn register and an INTTmn interrupt is generated.
Figure 6-28 Runtime Sequence (Capture Mode: Interval Measurement of Input Pulses).
TSmn(write)
TImn(input)
rising edge
start
trigger
detection
singal
TCR mn initial value
when MDmn0 = 1
edge detection
edge detection
note
0001
note
Note: When the clock is entered to TImn
(with a trigger) before starting, the count starts by detecting the trigger even if no
edge is detected, so the
capture value at the first capture ((4)) is not a pulse interval (in this case,
0001:
2
clock
intervals) and must be ignored.
Note: Because the first
count clock cycle runs after the
TSmn
bit is written and the start of the count is delayed before
the count clock is generated, an error of up to 1 clock cycle is generated. In addition, if information about starting
counting timing is required, the MDmn0 position is "1" so that an interrupt can be generated at the start of