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BAT32G1x9 user manual | Chapter 20 Serial interface IICA

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Rev.1.02

R/W
ACK

20.5.4

Ack (ACK).

The serial data status of the sender and receiver can be acknowledged by answer (ACK). The receiver returns

a reply each time it receives 8 bits of data.

Typically, the sender receives a reply after sending 8 bits of data. When the receiver returns the reply, it is deemed to

have been received normally and continues processing. Bit2 (ACKDn) can pass through the IICA status register n

(IICSn). Confirm the detection of the Ack. When the master receives the last data for the received state, a stop

condition is generated without returning a reply. When the slave does not return a reply after receiving the data, the

master device outputs a stop condition or a restart condition to abort the transmission. The reasons why a reply is

not returned are as follows:

①

There is no normal reception.

②

The receipt of the last data has ended.

③

The address specified receiver does not exist.

The receiver sets the SDAAn line low on the 9th clock to generate a reply (normal receive).

By setting the bit2 (ACKEn) of the IICA control register n0 (IICCTLn0) to "1", it becomes a state that automatically

generates a response. Sets bit3 (TRCn) of the IICSn register by the 8th bit of data that follows from the 7-bit address

information. In the case of receiving (TRCn=0,1), it is usually necessary to place the ACKEn position "1".

During the slave receive run (TRCn=0,1) cannot receive data or does not need the next data, the ACKEn must

be cleared to "0" to inform the master that the data cannot be received.

When the next data is not needed during the master receive run (TRCn=0,1), in order not to generate a reply,

the ACKEn bit must be cleared to "0" to notify the subordinate sender of the end of the data (stop sending).

Figure 20-16

Ack

SCLAn

SDAAn

When the address of the local station is received, regardless of the value of the ACKEn bit, a reply is

automatically generated; When an address for a non-local station is received, no reply (NACK) is generated.

When the extension code is received, a reply is generated by placing the ACKEn position "1" in advance. The

Ack generation method when receiving data varies depending on the waiting timing setting, as shown below.

•

When selecting a wait for 8 clocks (bit3 (WTIMn) = 0 of the IICCTLn0 register): pass before releasing the

wait ACKEn position "1" generates a reply synchronously with the 8th clock drop edge of the SCLAn pin.

•

When selecting a wait for 9 clocks (bit3 (WTIMn) = 1 of the IICCTLn0 register): pass beforehand ACKEn

position "1" to generate a reply.

Note: n=0,1

Summary of Contents for BAT32G1 9 Series

Page 1: ...tion of any damage to the company The name of Cmsemicron Limited and logo are both trademarks of our company Our company preserve the rights to further elaborate on the improvements about products function reliability and design in this manual However our company is not responsible for any usage about this munal The applications and their purposes in this manual are just for clarification our comp...

Page 2: ...9xx BAT32G139_datasheet_vx x pdf BAT32G179xx BAT32G179_datasheet_vx x pdf Usually in the early stage of chip selection the first thing to see is to look at the data sheet to evaluate whether the product can meet the functional requirements of the design After basically selecting the required product it is necessary to check the technical reference manual to determine whether the working mode of ea...

Page 3: ...hapter 14 Watchdog Timer Chapter 15 A D Converter Chapter 16 D A Converters Chapter 17 Comparator Chapter 18 Programmable Gain Amplifier Chapter 19 Universal Serial Communication Unit Chapter 20 Serial Interface IICA Chapter 21 Serial Interface SPI Chapter 22 CAN Control Chapter 23 LCD Bus Interface Chapter 24 Enhanced DMA Chapter 25 Linkage Controller Chapter 26 Interrupt function Chapter 27 Key ...

Page 4: ...ode Control Register PMCxx 40 2 3 9 Port read back register PREADxx 41 2 3 10 Peripheral I O redirect register 0 PIOR0 42 2 3 11 Peripheral I O redirect register 1 PIOR1 43 2 3 12 Peripheral I O redirect register 2 PIOR2 44 2 3 13 Peripheral I O redirect register 3 PIOR3 45 2 3 14 Peripheral I O redirect register 4 PIOR4 46 2 3 15 Global Digital Input Disable Register GDIDIS 47 2 4 Unused pin hand...

Page 5: ...llator 100 4 4 4 Low speed internal oscillator 100 4 5 Clock generation circuit operation 101 4 6 Clock control 103 4 6 1 Example of setting up a high speed internal oscillator 103 4 6 2 Example of setting up the X1 oscillation circuit 105 4 6 3 Example of setting up the XT1 oscillation circuit 106 4 6 4 State transition graph of the CPU clock 107 4 6 5 Conditions before CPU clock transfer and pro...

Page 6: ...imer unit 146 6 3 1 Peripheral enable register 0 PER0 147 6 3 2 Timer clock selection register m TPSm 148 6 3 3 Timer mode register mn TMRmn 151 6 3 4 Timer status register mn TSRmn 155 6 3 5 Timer channel enable status register m TEm 156 6 3 6 Timer channel start register m TSm 157 6 3 7 Timer channel stop register m TTm 158 6 3 8 Timer input and output selection register TIOS0 159 6 3 9 Timer ou...

Page 7: ...l event counter 193 6 8 3 Operation as a divider 196 6 8 4 Operation as input pulse interval measurements 199 6 8 5 Operation as input signal high and low level width measurements 202 6 8 6 Runs as a delay counter 206 6 9 Multi channel linkage operation function of the universal timer unit 209 6 9 1 Operation as a single trigger pulse output function 209 6 9 2 Operates as a PWM function 216 6 9 3 ...

Page 8: ...steps for deep sleep mode event counter mode 255 7 5 9 Functional limitations in deep sleep mode event counter mode only 255 7 5 10 Forced count stop via the TSTOP bit 255 7 5 11 Digital filters 255 7 5 12 The case where fIL is selected as the count source 255 Chapter 8 Timer B 256 8 1 Function of timer B 256 8 2 Structure of timer B 257 8 3 Control registers of timer B 258 8 3 1 Peripheral enable...

Page 9: ... Peripheral enable register 1 PER1 299 9 3 2 Timer C count register TC 300 9 3 3 Timer C count buffer register TCBUF 300 9 3 4 Timer C controls register 1 TCCR1 301 9 3 5 Timer C controls register 1 TCCR2 302 9 3 6 Timer C status register TCSR 303 9 4 Operation of timer C 304 9 4 1 Count the sources 304 9 4 2 Timer C starts counting the actions 304 9 4 3 Timer C counts stopped actions 307 9 4 4 En...

Page 10: ...le register i TMIERi i 0 1 350 10 3 17 The timer MPWM function outputs level control register i TMPOCRi i 0 1 351 10 3 18 Timer M counter i TMi i 0 1 352 10 3 19 Timer M General Purpose registers Ai Bi Ci Di 354 10 3 20 Port mode registers PMxx PMCxx 364 10 4 Common things about multiple patterns 365 10 4 1 Counting sources 365 10 4 2 The buffer operation 366 10 4 3 Synchronous Operation 369 10 4 ...

Page 11: ...gister SEC 447 11 3 7 Minute Count Register MIN 447 11 3 8 Hour Count Register HOUR 448 11 3 9 Day count register DAY 450 11 3 10 Week Count Register WEEK 451 11 3 11 Month count register MONTH 452 11 3 12 Year Count Register YEAR 452 11 3 13 Alarm clock minute register ALARMWM 453 11 3 14 Alarm hour register ALARMWH 453 11 3 15 Alarm Clock Week Register ALARMWW 453 11 3 16 Port mode registers and...

Page 12: ...ontrol circuitry 473 Chapter 14 Watchdog timer 474 14 1 The function of the watchdog timer 474 14 2 Structure of the watchdog timer 474 14 3 Control registers of the watchdog timer 476 14 3 1 The Watchdog Timer s enable Register WDTE 476 14 3 2 LockUP Control Register LOCKCTL and its Protection Register PRCR 477 14 3 3 WDTCFG Configuration Register WDTCFG0 1 2 3 478 14 4 Operation of the watchdog ...

Page 13: ...mode 512 15 4 6 Hardware triggered no wait mode select mode single shot transition mode 513 15 4 7 Hardware triggered no wait mode scan mode continuous transition mode 514 15 4 8 Hardware triggered no wait mode scan mode single shot conversion mode 515 15 4 9 Hardware triggered wait mode selection mode continuous transition mode 516 15 4 10 Hardware triggered wait mode select mode single shot tran...

Page 14: ...e input signal of comparator 1 selects the control register CMPSEL1 547 17 3 9 Hysteresis control register CMP0HY for comparator 0 548 17 3 10 Hysteresis control register CMP1HY for comparator 1 549 17 3 11 Registers that control the function of the analog input pin port 550 17 4 Run the instructions 551 17 4 10 The digital filter of comparator i i 0 1 553 17 4 11 Comparator i interrupt i 0 1 553 ...

Page 15: ... i e m 1 2 583 19 3 7 The serial flag clears the trigger register mn SIRmn 584 19 3 8 Serial status register mn SSRmn 585 19 3 9 Serial channel start register m SSm 587 19 3 10 Serial channel stop register m STm 588 19 3 11 Serial channel enable status register m SEm 589 19 3 12 Serial output enable register m SOEm 590 19 3 13 Serial output register m SOm 591 19 3 14 Serial output level register m...

Page 16: ... 704 19 8 1 LIN sends 704 19 8 2 LIN receives 707 19 9 Simple I2C IIC00 IIC01 IIC10 IIC11 IIC20 Operation of IIC21 IIC30 IIC31 communication 712 19 9 1 The address segment is sent 713 19 9 2 Data sending 718 19 9 3 Data reception 721 19 9 4 Stop conditions generation 725 19 9 5 Calculation of the transfer rate 726 19 9 6 In simple I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31 Processing step...

Page 17: ...WHn 749 20 3 8 Port mode register x PMx 750 20 4 The functionality of I2C bus mode 751 20 4 1 Pin structure 751 20 4 2 The method of transmitting the clock is set by the IICWLn register and the IICWHn register 752 20 5 Definition and control method of theI2C bus 753 20 5 1 Start conditions 754 20 5 2 address 755 20 5 3 The designation of the transmission direction 755 20 5 4 Ack ACK 756 20 5 5 Sto...

Page 18: ... 2 The reception of the master 829 21 4 3 Slave sending and receiving 832 21 4 4 Slave reception 835 Chapter 22 CAN control 838 22 1 Summary description 838 22 1 1 features 838 22 1 2 Feature overview 839 22 1 3 Configuration 840 22 2 CAN protocol 841 22 2 1 Frame format 841 22 2 2 Frame type 842 22 2 3 Data frames and remote frames 842 22 2 4 Error frame 849 22 2 5 Overload frames 850 22 3 functi...

Page 19: ...7 15 CAN module last entered the pointer register CnLIPT 907 22 7 16 CAN module receive History List Register CnRGPT 908 22 7 17 CAN module last output pointer register CnLOPT 909 22 7 18 CAN module send History List Register CnTGPT 910 22 7 19 CAN Module Timestamp Register CnTS 911 22 7 20 CAN message data byte register CnMDBxm x 0 to 7 CnMDBzm z 01 23 45 67 913 22 7 21 CAN message data length re...

Page 20: ...e 947 22 14 Timestamp function 948 22 14 1 Timestamp function 948 22 15 Baud rate setting 950 22 15 1 Baud rate setting 950 22 15 2 A representative example of baud rate settings 954 22 16 The operation of the CAN controller 958 Chapter 23 LCD bus interface 983 23 1 Functions of the LCD bus interface 983 23 2 LCD bus interface configuration 984 23 2 1 LCD bus interface data register LBDATA LBDATAL...

Page 21: ...24 3 7 DMA transmit count register j DMACTj j 0 39 1021 24 3 8 DMA number of transfers reloads register j DMRLDj j 0 39 1022 24 3 9 DMA source address register j DMSARj j 0 39 1023 24 3 10 DMA destination address register j DMDARj j 0 39 1023 24 3 11 DMA boot enable register i DMAENi i 0 4 1024 24 3 12 DMAENi position register DMSETi 1026 24 3 13 DMAENi reset register DMCLRi 1026 24 3 14 DMA Base ...

Page 22: ...4 26 4 2 Acceptance of unaskable interrupt requests 1064 Chapter 27 Key interrupt function 1065 27 1 The function of the key interrupt 1065 27 2 The structure of the key interrupt 1065 27 3 Control Registers of key interrupts 1067 27 3 1 Key return mode register KRM 1067 27 3 2 Port mode register PMx 1068 Chapter 28 Standby function 1069 28 1 Standby function 1069 28 2 Sleep mode 1070 28 2 1 The s...

Page 23: ... 3 3 RAM parity error detection function 1117 32 3 4 SFR protection function 1119 32 3 5 Frequency detection function 1120 32 3 6 A D test function 1121 32 3 7 Digital output signal level detection function on input output pins 1124 32 3 8 Product unique identifier registers 1125 Chapter 33 Temperature sensor and internal reference voltage 1126 33 1 Temperature sensor 1126 33 2 Registers for tempe...

Page 24: ...ster FLOPMD1 FLOPMD2 1142 35 3 3 Flash Erase Control Register FLERMD 1142 35 3 4 Flash Status Register FLSTS 1143 35 3 5 Flash full chip erase time control register FLCERCNT 1143 35 3 6 Flash Page Erase Time Control Register FLSERCNT 1144 35 3 7 Flash Write Time Control Register FLPROCNT 1145 35 3 8 Flash Wipe And Write Protection Control Register FLSECPR 1146 35 4 Flash operation method 1147 35 4...

Page 25: ...ontroller NVIC 1 Unshielded Interrupt NMI Supports 32 maskable interrupt requests IRQs 4 interrupt priorities The system timer SysTick is a 24 bit countdown timer with the option of fCLK or fIL counting clocks Vector Table Offset Register VTOR The software can write the VTOR to relocate the vector table start address to a different location Default value of this register is 0x0000_0000 low 8 bits ...

Page 26: ...ev 1 02 Figure 1 1 Debug block diagram of Cortex M0 Note SWD does not work in Deep Sleep mode please debug in active and sleep modes bus matrix Cortex M0 core SW DP Bridge NVIC DWT BPU system bus Cortex M0 debug support MCUdebug support SWDIO SWCLK DBGMCU AHB AP ...

Page 27: ...g the debugger the P40 cannot be used as a GPIO because the ENO and DOT of the IOBOF are controlled by the debugger at this time 1 The SWD debug interface is disabled The P40 can be used as a GPIO FRZEN0 When the debugger is connected and the CPU is in the debug state HALTED 1 the timer peripheral module action stop Note 1 0 Peripheral action 1 Peripheral Stops FRZEN1 When the debugger is connecte...

Page 28: ...debugging features built into the Cortex M0 core are part of the ARM CoreSight design suite For related documents please refer to Cortex M0 Technical Reference Manual TRM ARM debug interface V5 ARM CoreSight Design Kit Version R1p1 Technical Reference Manual ARM CoreSight MTB M0 Technical Reference Manual ...

Page 29: ...nual Chapter 2 Pin function www mcu com cn 29 1149 Rev 1 02 Chapter 2 Pin function 2 1 Port capabilities Refer to datasheet for each product range 2 2 Port multiplexing function Refer to datasheet for each product range ...

Page 30: ...U00 POM00 PMC00 Note 1 PREAD00 1 PM01 P01 PSET01 PCLR01 PU01 PIM01 PMC01 Note 1 PREAD01 2 PM02 P02 PSET02 PCLR02 PU02 POM02 PMC02 PREAD02 3 PM03 P03 PSET03 PCLR03 PU03 PIM03 POM03 PMC03 PREAD03 4 PM04 P04 PSET04 PCLR04 PU04 PIM04 POM04 PMC04 PREAD04 5 PM05 P05 PSET05 PCLR05 PU05 PREAD05 6 PM06 P06 PSET06 PCLR06 PU06 PREAD06 Port 1 0 PM10 P10 PSET10 PCLR10 PU10 PIM10 POM10 PMC10 PREAD10 1 PM11 P11 ...

Page 31: ...4 5 PM55 P55 PSET55 PCLR55 PU55 PIM55 POM55 PREAD55 6 PM56 P56 PSET56 PCLR56 PU56 PREAD56 7 PM57 P57 PSET57 PCLR57 PU57 PREAD57 Port 6 0 PM60 P60 PSET60 PCLR60 PREAD60 1 PM61 P61 PSET61 PCLR61 PREAD61 2 PM62 P62 PSET62 PCLR62 PREAD62 3 PM63 P63 PSET63 PCLR63 PREAD63 4 PM64 P64 PSET64 PCLR64 PU64 PREAD64 5 PM65 P65 PSET65 PCLR65 PU65 PREAD65 6 PM66 P66 PSET66 PCLR66 PU66 PREAD66 7 PM67 P67 PSET67 P...

Page 32: ...6 PMC136 Note 1 PREAD136 7 PM137 P137 PSET137 PCLR137 PU137 PREAD137 Port 14 0 PM140 P140 PSET140 PCLR140 PU140 PREAD140 1 PM141 P141 PSET141 PCLR141 PU141 PREAD141 2 PM142 P142 PSET142 PCLR142 PU142 PIM142 POM142 PREAD142 3 PM143 P143 PSET143 PCLR143 PU143 PIM143 POM143 PREAD143 4 PM144 P144 PSET144 PCLR144 PU144 POM144 PMC144 PREAD144 5 PM145 P145 PSET145 PCLR145 PU145 PMC145 PREAD145 6 PM146 P1...

Page 33: ... PM11 PM10 0x321 FFH R W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 0x322 FFH R W PM3 1 1 1 1 1 1 PM31 PM30 0x323 FFH R W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 0x324 FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 0x325 FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 0x326 FFH R W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 0x327 FFH R W PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 0...

Page 34: ...3 0 0 0 0 0 0 P31 P30 0x303 00H output latch R W P4 P47 P46 P45 P44 P43 P42 P41 P40 0x304 00H output latch R W P5 P57 P56 P55 P54 P53 P52 P51 P50 0x305 00H output latch R W P6 P67 P66 P65 P64 P63 P62 P61 P60 0x306 00H output latch R W P7 P77 P76 P75 P74 P73 P72 P71 P70 0x307 00H output latch R W P8 P87 P86 P85 P84 P83 P82 P81 P80 0x308 00H output latch R W P10 0 0 0 0 0 P102 P101 P100 0x30A 00H ou...

Page 35: ...T20 0x082 00H In PSET3 0 0 0 0 0 0 PSET31 PSET30 0x083 00H In PSET4 PSET47 PSET46 PSET45 PSET44 PSET43 PSET42 PSET41 PSET40 0x084 00H In PSET5 PSET57 PSET56 PSET55 PSET54 PSET53 PSET52 PSET51 PSET50 0x085 00H In PSET6 PSET67 PSET66 PSET65 PSET64 PSET63 PSET62 PSET61 PSET60 0x086 00H In PSET7 PSET77 PSET76 PSET75 PSET74 PSET73 PSET72 PSET71 PSET70 0x087 00H In PSET8 PSET87 PSET86 PSET85 PSET84 PSET...

Page 36: ... 00H In PCLR3 0 0 0 0 0 0 PCLR31 PCLR30 0x093 00H In PCLR4 PCLR47 PCLR46 PCLR45 PCLR44 PCLR43 PCLR42 PCLR41 PCLR40 0x094 00H In PCLR5 PCLR57 PCLR56 PCLR55 PCLR54 PCLR53 PCLR52 PCLR51 PCLR50 0x095 00H In PCLR6 PCLR67 PCLR66 PCLR65 PCLR64 PCLR63 PCLR62 PCLR61 PCLR60 0x096 00H In PCLR7 PCLR77 PCLR76 PCLR75 PCLR74 PCLR73 PCLR72 PCLR71 PCLR70 0x097 00H In PCLR8 PCLR87 PCLR86 PCLR85 PCLR84 PCLR83 PCLR82...

Page 37: ...U register is 0x40040000 and the offset address is shown in the figure below Figure2 5 Format of pull up resistor selection register symbol 7 6 5 4 3 2 1 0 Offset address After reset R W PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 0x030 00H R W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 0x031 00H R W PU3 0 0 0 0 0 0 PU31 PU30 0x033 00H R W PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40 0x034 01H R W PU5 PU57...

Page 38: ...ister is 0x40040000 and the partial address is shown in the figure below Figure2 6 format of port input mode register symbol 7 6 5 4 3 2 1 0 Offset address After reset R W PIM0 0 0 0 PIM04 PIM03 0 PIM01 0 0x040 00H R W PIM1 PIM17 PIM16 PIM15 PIM14 0 0 0 PIM10 0x041 00H R W PIM3 0 0 0 0 0 0 0 PIM30 0x043 00H R W PIM4 0 0 0 PIM44 PIM43 0 0 0 0x044 00H R W PIM5 0 0 PIM55 0 0 0 0 PIM50 0x045 00H R W P...

Page 39: ...s is shown in the figure below Note that for bits that set the N channel open drain output mode POMmn 1 no internal pull up resistor is connected Figure2 7 format of port output mode register symbol 7 6 5 4 3 2 1 0 Offset address After reset R W POM0 0 0 0 POM04 POM03 POM02 0 POM00 0x050 00H R W POM1 POM17 0 POM15 POM14 POM13 0 POM11 POM10 0x051 00H R W POM3 0 0 0 0 0 0 0 POM30 0x053 00H R W POM4 ...

Page 40: ...fter reset R W PMC0 1 1 1 PMC04 PMC03 PMC02 1 1 0x060 FFH R W PMC1 1 1 1 1 1 1 PMC11 PMC10 0x061 FFH R W PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 0x062 FFH R W PMC10 1 1 1 1 1 PMC102 PMC101 PMC100 0x06A FFH R W PMC12 1 1 1 1 1 1 1 PMC120 0x06C FFH R W PMC13 1 PMC136 Note 1 1 1 1 1 1 0 0x06D FEH R W PMC14 PMC147 PMC146 PMC145 PMC144 1 1 1 1 0x06E FFH R W PMC15 1 PMC156 PMC155 PMC154 PMC...

Page 41: ...DC47PREADC46PREADC45PREADC44 PREAD43 PREAD42 PREAD41 PREAD40 0x0A4 xxH R PREAD5 PREAD57 PREAD56 PREAD55 PREAD54 PREAD53 PREAD52 PREAD51 PREAD50 0x0A5 xxH R PREAD6 PREAD67 PREAD66 PREAD65 PREAD64 PREAD63 PREAD62 PREAD61 PREAD60 0x0A6 xxH R PREAD7 PREAD77 PREAD76 PREAD75 PREAD74 PREAD73 PREAD72 PREAD71 PREAD70 0x0A7 xxH R PREAD8 PREAD87 PREAD86 PREAD85 PREAD84 PREAD83 PREAD82 PREAD81 PREAD80 0x0A8 x...

Page 42: ...IOR07 INTP8 P74 P42 P00 P74 P00 INTP10 P76 P05 P01 must be set to 0 initial value INTP11 P77 P06 P20 bit6 PIOR06 RxD2 must be set to 0 initial value P14 P14 TxD2 P13 P10 SCL20 P15 SDA20 P14 SDI20 P14 SDO20 P13 SCLK20 P15 bit5 PIOR05 RXD1 P01 P73 TXD1 P00 P72 bit4 PIOR04 CLKBUZ1 P141 P55 must be set to 0 initial value INTP5 P16 P12 bit3 PIOR03 CLKBUZ0 P140 P31 P140 P31 bit2 PIOR02 SCLA0 P60 P14 P60...

Page 43: ...witches ports that are assigned a multiplexing function After generating a reset signal the value of this register changes to 00H Figure2 11 Format of peripheral I O redirect register 1 PIOR1 Address 0x40040879H After reset 00HR W SYMBOL 7 6 5 4 3 2 1 0 PIOR1 PIOR13 PIOR12 Timer A s TAO pin selection 0 0 and P30 multiplexing 0 1 and P50 multiplexed 1 0 and P00 multiplexed 1 1 Disable settings PIOR...

Page 44: ...6 Disable setting bit6 PIOR26 TMIOD0 P15 P17 PIOR36 PIOR37 must both be configured as 0 bit5 PIOR25 TMIOD1 P11 P51 PIOR36 PIOR37 must both be configured as 0 bit4 PIOR24 TMIOC1 P13 P50 PIOR36 PIOR37 must both be configured as 0 bit3 PIOR23 TMIOB1 P10 P30 PIOR36 PIOR37 must both be configured as 0 bit2 PIOR22 TMIOA1 P12 P16 PIOR36 PIOR37 must both be configured as 0 bit1 PIOR21 VCOUT1 P31 P70 PIOR3...

Page 45: ...ss 0x4004087C after reset 00HR W SYMBOL 7 6 5 4 3 2 1 0 WORST3 PIOR3 Features Set Values 0 1 bit5 PIOR35 TXD0 PIOR34 Control P12 RXD0 PIOR34 Control P11 bit4 PIOR34 TXD0 PIOR01 Control P40 RXD0 PIOR01 Control P137 bit3 PIOR33 CRXD0 P03 P50 CTXD0 P02 P51 bit2 PIOR32 VCOUT1 Output L PIOR21 Control bit1 PIOR31 VCOUT0 输出L PIOR20 Control PIOR37 PIOR36 TMIOA0 TMIOB0 TMIOC0 TMIOD0 TMIOA1 TMIOB1 TMIOC1 TM...

Page 46: ...er 4 PIOR4 Address 0x40040874 After reset 00HR W SYMBOL 7 6 5 4 3 2 1 0 PIOR4 0 1 TI14 TO14 P100 P42 TI15 TO15 P110 P46 TI16 TO16 P111 P102 TI17 TO17 P05 P145 SCLK31 SCL31 P43 P54 SDI31 P44 P53 SDO31 P45 P52 SDA31 P44 P53 INTP1 PIOR0 0 control P56 INTP2 PIOR0 0 control P47 INTP3 PIOR0 0 control P57 INTP4 PIOR0 0 control P146 INTP6 P140 P84 INTP7 P141 P85 INTP8 PIOR0 7 P86 INTP9 PIOR0 0 control P87...

Page 47: ... input buffer of the EVDD power supply 0 Input to the input buffer is allowed default 1 Disable input to the input buffer Prevents leakage current flowing through the input buffer To power off an EVDD you must follow these steps to set it up 1 Set to disable the input buffer input GDIDIS0 1 2 Cut off the power supply to the EVDD To power up the EVDD you must follow these steps to set it up 1 Turn ...

Page 48: ...Set the output latch of the port to 0 and set it to open or set the output latch of the port to 1 and connect the EVDD or via resistors alone EVSS P63 P67 Input Separately connect the EVDD or EVSS via resistors Output Set to open circuit P70 P77 P80 P87 P100 P102 P110 P111 P120 P121 P124 input Separately connect VDD or VSS via resistors P130 output Set to open circuit P136 Input Output Input Separ...

Page 49: ...unctions or multiplexing functions the unused multiplexing functions cannot affect the output of the functions to be used The basic idea of the setting at this time is shown in Table2 3 basic Figure2 16 The basic structure of the output circuit of the pin GPIO Combined function Note 1 When there is no POM register this signal is Low level 0 2 When there is no multiplexing function this signal is h...

Page 50: ...BCLK1 input 1 TAIO input PIOR13 PIOR12 00B 1 output 0 0 TO00 0 INTP10 input PIOR07 1 PIOR41 0 1 P02 P02 input 0 1 output 0 0 0 0 1 TxD1 SDO10 1 CTxD0 1 N channel open drain output 1 0 0 0 1 ANI11 Analog input 1 1 TxD1 output PIOR45 0 0 1 0 0 1 CTxD0 1 SDO10 output PIOR45 0 0 1 0 0 1 CTxD0 1 VCIN10 Analog input 1 1 CTxD0 output PIOR33 0 0 1 0 0 1 TxD1 SDO10 1 P03 P03 input 0 1 output 0 0 0 0 1 SDA1...

Page 51: ...1 output 0 0 0 0 1 SDA11 1 TMIOD1 0 TMIOA1 0 TMIOC1 0 N channel open drain output 1 0 0 0 1 ANI8 Analog input 1 1 SDI11 input 0 1 SDA11 Input Outpu t 1 0 0 1 TMIOD1 0 TMIOA1 0 TMIOC1 0 RxD0 input PIOR35 1 0 1 1 TMIOD1 input Please refer to the register instructions for PIOR2 and PIOR3 for configuration 0 1 output 0 0 0 0 SDA11 1 TMIOA1 input Please refer to the register instructions for PIOR2 and ...

Page 52: ...en drain output 1 0 0 1 RxD2 input PIOR01 0 1 SDI20 input PIOR01 0 1 SDA20 Input Outpu t PIOR01 0 1 0 1 TMIOB0 0 TMIOC1 0 TMIOD0 0 SCLA0 0 TMIOB0 input Please refer to the register instructions for PIOR2 and PIOR3 for configuration 1 output 1 0 0 SDA20 1 SCLA0 0 TMIOC1 input Please refer to the register instructions for PIOR2 and PIOR3 for configuration 1 output 1 0 0 SDA20 1 SCLA0 0 TMIOD0 input ...

Page 53: ...R01 1 PIOR34 0 PIOR35 0 1 TMIOA1 input Please refer to the register instructions for PIOR2 and PIOR3 for configuration 1 output 0 0 TO01 0 TMIOC0 0 P17 P17 input 1 output 0 0 0 1 TxD0 SDO00 1 TO02 0 TMIOA0 0 TMIOD0 0 N channel drain Open output 1 0 0 1 TI02 input 1 TO02 output 0 0 0 TxD0 SDO00 1 TMIOA0 0 TMIOD0 0 TMIOA0 input Please refer to the register instructions for PIOR2 and PIOR3 for config...

Page 54: ...BYREFM Reference input 1 1 VCIN13 Analog input 1 1 P22 P22 input 0 1 output 0 0 0 1 ANI2 Analog input 1 1 ANO0 Analog output 1 1 VCIN0 Analog input 1 1 PGA0IN Analog input 1 1 P23 P23 input 0 1 output 0 0 0 1 ANI3 Analog input 1 1 ANO1 Analog output 1 1 PGA0GND Analog input 1 1 P24 P24 input 0 1 output 0 0 0 1 ANI4 Analog input 1 1 PGA1IN Analog input 1 1 P25 P25 input 0 1 output 0 0 0 1 ANI5 Anal...

Page 55: ...K00 input PIOR01 0 1 output 0 1 0 0 RTC1HZ 0 TAO 0 TMIOB1 0 SCL00 output PIOR01 0 0 1 0 0 RTC1HZ 0 TAO 0 TMIOB1 0 MAN output PIOR13 PIOR12 00B 0 0 0 SCLK00 SCL00 1 RTC1HZ 0 TMIOB1 0 TMIOB1 input Please refer to the register instructions for PIOR2 and PIOR3 for configuration 1 output 0 0 0 SCLK00 SCL00 1 RTC1HZ 0 TAO 0 P31 P31 input 1 output 0 0 1 TO03 0 VCOUT1 0 CLKBUZ0 0 TAIO 0 TI03 input 1 TO03 ...

Page 56: ...NTP8 input PIOR00 1 PIOR07 0 PIOR45 0 1 TI14 input PIOR47 1 1 TO14 output PIOR47 1 0 0 P43 P43 input 1 output 0 0 0 1 SCLK31 SCL31 1 N channel open drain output 1 0 0 1 INTP9 input PIOR00 1 PIOR45 0 1 SCLK31 input PIOR46 0 1 output PIOR46 0 0 1 0 1 SCL31 output PIOR46 0 0 1 0 1 P44 P44 input 1 output 0 0 0 1 SDA31 1 N channel open drain output 1 0 0 1 SDI31 input PIOR46 0 1 SDA31 Input Output PIOR...

Page 57: ... configuration 1 output 0 0 0 TBIO0 0 TAO 0 P51 P51 input 1 output 0 0 0 1 TxD0 SDO00 1 CTxD0 1 TBIO1 0 TMIOD1 0 N channel open drain output 1 0 0 1 INTP2 input PIOR00 0 PIOR45 0 1 SDO00 output PIOR01 0 PIOR34 0 PIOR35 0 0 1 0 1 CTxD0 1 TBIO1 0 TMIOD1 0 TxD0 output PIOR01 0 PIOR34 0 PIOR35 0 0 1 0 1 CTxD0 1 TBIO1 0 TMIOD1 0 CTxD0 output PIOR33 1 0 1 0 1 TxD0 SDO00 1 TBIO1 0 TMIOD1 0 TBIO1 input 1 ...

Page 58: ...BAT32G1x9 user manual Chapter 2 Pin function www mcu com cn 58 1149 Rev 1 02 SCLK31 input PIOR46 1 1 output PIOR46 1 0 1 0 1 SCL31 output PIOR46 1 0 1 0 1 ...

Page 59: ...1 SCLK00 1 CLKBUZ1 0 SPIHS0_SCK 0 N channel open drain output 1 0 0 1 SPIHS0_SC K input 1 output 0 0 0 SCLK00 1 CLKBUZ1 0 INTP4 input PIOR00 1 PIOR45 0 1 CLKBUZ1 output PIOR04 1 0 0 0 SCLK00 1 SPIHS0_SCK 0 SCLK00 input PIOR01 1 1 output 0 1 0 1 CLKBUZ1 0 SPIHS0_SCK 0 P56 P56 input 1 output 0 0 1 SPIHS0_SO 0 INTP1 input PIOR45 1 1 SPIHS0_MI input 1 SPIHS0_SO output 0 0 P57 P57 input 1 output 0 0 1 ...

Page 60: ...tput 6V withstand voltage 0 0 1 SDAA0 0 SDAA0 Input Output PIOR02 0 0 0 P62 P62 input 1 N channel open drain output 6V withstand voltage 0 0 1 SCLA1 0 SS00 input 1 SCLA1 Input Output 0 0 P63 P63 input 1 N channel open drain output 6V withstand voltage 0 0 1 SDAA1 0 SDAA1 Input Output 0 0 P64 P64 input 1 output 0 0 1 CTxD1 1 TO10 0 TI10 input 1 TO10 output 0 0 CTxD1 output 0 1 TO10 0 P65 P65 input ...

Page 61: ...rain output 1 0 0 1 KR1 input 1 SDI21 input 1 SDA21 Input Output 0 1 0 1 VCOUT0 0 INCOUT0 output PIOR20 1 0 0 0 SDA21 1 P72 P72 input 1 output 0 0 1 SDO21 1 KR2 input 1 SDO21 output 0 1 P73 P73 input 1 output 0 0 1 SDO01 1 KR3 input 1 SDO01 output 0 1 P74 P74 input 1 output 0 0 0 1 SDA01 1 N channel open drain output 1 0 0 1 KR4 input 1 INTP8 input PIOR00 0 PIOR07 0 PIOR45 0 1 SDI01 input 1 SDA01 ...

Page 62: ...BAT32G1x9 user manual Chapter 2 Pin function www mcu com cn 62 1149 Rev 1 02 output 0 0 1 TxD2 IrTxD 1 KR7 input 1 INTP11 input PIOR01 0 PIOR07 0 PIOR41 0 1 TxD2 IrTxd output PIOR01 1 0 1 ...

Page 63: ...1 0 N channel open drain output 1 0 0 1 DBD1 output 0 1 0 SDA10 1 SDI10 input PIOR45 1 1 SDA10 Input Output PIOR45 1 0 1 0 1 DBD1 0 RxD1 input PIOR45 1 1 P82 P82 input 1 output 0 0 0 1 SDO10 TxD1 1 DBD2 0 N channel open drain output 1 0 0 1 DBD2 output 0 1 0 SDO10 TxD1 1 SDO10 output PIOR45 1 0 1 0 1 DBD2 0 TxD1 output PIOR45 1 0 1 0 1 DBD2 0 P83 P83 input 1 output 0 0 1 DBD3 0 DBD3 output 1 0 P84...

Page 64: ...R47 0 0 1 TO14 output PIOR47 0 0 0 0 P101 P101 input 0 1 output 0 0 0 1 ANI24 Analog input 1 1 P102 P102 input 0 1 output 0 0 0 1 TO16 0 ANI25 Analog input 1 1 TI16 input PIOR47 1 0 1 TO16 output PIOR47 1 0 0 0 P110 P110 input 1 output 0 0 1 TO15 0 TI15 input PIOR47 0 1 TO15 output PIOR47 0 0 0 INTP10 input PIOR41 1 1 P111 P111 input 1 output 0 0 1 TO16 0 TI16 input PIOR47 0 1 TO16 output PIOR47 0...

Page 65: ...24 input xx00 xx10 xx11 XT2 xx01 EXCLKS input xx11 Pin name Features used PIORx POMxx PMCxx PMxx Pxx The output of the multiplexing function Feature name Input Output The output function of SCI CAN Outside of SCI CAN P130 P130 output 0 1 P136 P136 input 0 Note 2 1 output 0 Note 2 0 0 1 INTP0 Note 1 input 1 P137 P137 input 1 output 0 0 1 INTP0 Note 2 input 1 SWCLK input 1 RxD0 input PIOR34 1 PIOR35...

Page 66: ...input 1 output 0 1 0 1 SPIHS1_SCK 0 SCL30 output 0 1 0 1 SPIHS1_SCK 0 P143 P143 input 1 output 0 0 0 1 SDA30 1 SPIHS1_SO 0 N channel open drain output 1 0 0 1 SPIHS1_MI input 1 SPIHS1_SO output 0 0 0 SDA30 1 SDI30 input 1 SDA30 Input Outp ut 1 0 1 SPIHS1_SO 0 RxD3 input 1 P144 P144 input 0 1 output 0 0 0 0 1 TxD3 SDO30 1 SPIHS1_MO 0 N channel open drain output 1 0 0 0 1 ANI26 Analog input 1 1 SPIH...

Page 67: ... 0 0 1 ANI17 Analog input 1 1 P151 P151 input 0 1 output 0 0 0 1 ANI18 Analog input 1 1 P152 P152 input 0 1 output 0 0 0 1 ANI19 Analog input 1 1 P153 P153 input 0 1 output 0 0 0 1 ANI20 Analog input 1 1 P154 P154 input 0 1 output 0 0 0 1 ANI21 Analog input 1 1 P155 P155 input 0 1 output 0 0 0 1 ANI22 Analog input 1 1 P156 P156 input 0 1 output 0 0 0 1 ANI23 Analog input 1 1 ...

Page 68: ...ipheral hardware APB bus DMA bus system bus System Bus This bus connects the system bus peripheral bus of the Cortex M0 core to a bus matrix that coordinates access between the core and the DMA DMA bus This bus connects the DMA s AHB master interface to a bus matrix that coordinates CPU and DMA access to SRAM flash memory and peripherals Bus Matrix The bus matrix coordinates the access arbitration...

Page 69: ...gram of address area partition BAT32G139 reserve Cortex M0 specific resource region for peripherals reserve resource region for peripherals reserve SRAM 32KB reserve data flash 2 5KB reserve main flash region 256KB FFFF_FFFFH E00F_FFFFH E000_0000H 4005_FFFFH 4000_0000H 2000_7FFFH 2000_0000H 0050_09FFH 0050_0000H 0003_FFFFH 0000_0000H ...

Page 70: ...s area partition BAT32G179 reserve Cortex M0 specific resource region for peripherals reserve resource region for peripherals reserve SRAM 64KB reserve data flash 20KB reserve main flash region 512KB FFFF_FFFFH E00F_FFFFH E000_0000H 4005_FFFFH 4000_0000H 2000_FFFFH 2000_0000H 0050_4FFFH 0050_0000H 0007_FFFFH 0000_0000H ...

Page 71: ...BFF Serial interface IICA0 0x4004_1C00 0x4004_1FFF Timer4 0x4004_2000 0x4004_23FF Timer A 0x4004_2400 0x4004_27FF Timer B 0x4004_2800 0x4004_2BFF Timer M 0x4004_2C00 0x4004_2FFF Timer C 0x4004_3000 0x4004_33FF Universal CRC See Chapter 31 Safety Functions for details 0x4004_3400 0x4004_37FF Linkage controller 0x4004_3800 0x4004_3BFF Comparator 0x4004_3C00 0x4004_3FFF Timer M PWMOP 0x4004_4400 0x40...

Page 72: ...al oscillator clock Oscillation can be stopped by entering deep sleep mode or by setting the HIOSTOP bit bit0 of the CSC register The frequency of the option byte setting can be changed via the frequency selection register HOCODIV of the high speed internal oscillator For frequency settings refer to Figure 4 14 Format of Frequency Selection Register HOCODIV for the high speed internal oscillator41...

Page 73: ...ollowing peripheral hardware can run through a low speed internal oscillator clock Watchdog timer Real time clock 15 bit interval timer Timer A When the bit4 WDTON of theoption byte 000C0H orthe bit4 WUTMMCK0 of subsystem clock modecontrolregister OSMC is 1 the low speed internal oscillator oscillates However the WDTON bit is 1 and the WUTMMCK0 bit is 0 and the bit0 WDSTBYON of option byte 000C0H ...

Page 74: ...rol Register CKC Clock Operating State Control Register CSC The state register OSTC of the oscillation settling time counter Oscillation settling time selection register OSTS peripheral enable register 0 1 2 3 PER0 PER1 PER2 PER3 The subsystem clock provides a mode control register OSMC Frequency Selection Register HOCODIV for high speed internal oscillators Trimming Register HIOTRM for high speed...

Page 75: ...eed internal oscilator 15kHz TYP watchd og timer HOCODIV2 HOCODIV1 HOCODIV0 high speed internal oscilator frequency selection register HOCODIV XTSTOP HIOSTOP CL S clock operation status control register CSC HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 high speed internal oscilator trimming register HIOTRM 6 RTCLPC WUTMMCK0 secondary system clock provides mode control register OSMC PER0 RTC EN p...

Page 76: ...IH Clock frequency of high speed internal oscillator max 64MHz fEX External master system clock frequency fMX High speed system clock frequency fMAIN The master system clock frequency fXT XT1 clock oscillation frequency fEXS External subsystem clock frequency fSUB Subsystem clock frequency fCLK The clock frequency of the CPU peripheral hardware fII Clock frequency of low speed internal oscillator ...

Page 77: ...egisters OSMC Frequency Selection Register HOCODIV for high speed internal oscillators Trimming Register HIOTRM for high speed internal oscillator Note that the registers and bits assigned vary by product You must set an initial value for the unassigned bits 4 3 1 Clock operating mode control register CMC This is the register that sets the operating mode of the X1 P121 X2 EXCLK P122 XT1 P123 XT2 E...

Page 78: ...X1 clock 0 1MHz fX 10MHz 1 10MHz fX 20MHz Note The EXCLKS OSCSELS AMPHS1 and AMPHS0 bits are initialized only during power on reset while remaining unchanged at other resets Note 1 After the reset is released the CMC register can only be written once via the 8 bit memory operation instruction When using the CMC register at the initial value 00H in order to prevent the program from malfunctioning i...

Page 79: ... the high speed system clock fMX as the main system clock fMAIN Note 1 bit7 and bit5 are read only bits 2 It is forbidden to change the value of the MCM0 bit in the state of placing the CSS position 1 Note fHOCO The clock frequency of the high speed internal oscillator 64MHz maximum fIH Clock frequency of high speed internal oscillator 64MHz maximum fMX High speed system clock frequency fMAIN The ...

Page 80: ...nal shaker stop Note 1 After the reset is released the CSC register must be set after the clock operating mode control register CMC is set 2 After reset released and before placing the MSTOP position 0 the Oscillation Settling Time Selection Register OSTS must be set However when using the OSTS register at the initial value there is no need to set the OSTS register 3 To start the oscillation of X1...

Page 81: ...aster system clock FMX as the input clock source for the PLL PLLD1 PLLD0 PLL Divider selection 0 0 No Dividers 0 1 Divide by 2 1 x Divide by 4 PLLM PLL multiplication option 0 12 times 1 16 times PLLON PLL work enable 0 PLL turns off 1 PLL turns on When using PLL as the system clock the clock structure is shown in the following figure where m is 12 16 which is determined by the setting value of PL...

Page 82: ... subsystem clock and oscillation of the X1 clock begins When the CPU clock is a high speed internal oscillator clock and the X1 clock oscillates is shifted into deep sleep mode and then exited OSTC registers can be read via 8 bit memory operation instructions By the generation of a reset signal into deep sleep mode or the MSTOP bit bit7 of the Clock Operating State Control Register CSC set to 1 th...

Page 83: ...bove time the bits will change to 1 in turn starting from bit MOST8 and remain in the state of 1 2 The Oscillation Settling Time Counter only counts within the Oscillation Settling Time Select Register OSTS set by the Oscillation Settling Time Register OSTS In the following cases the setting value of the oscillation settling time of the OSTS register must be greater than the count value confirmed ...

Page 84: ...he selection of oscillation stabilization time fX 10MHz fX 20MHz 0 0 0 28 fX 25 6us 12 8us 0 0 1 29 fX 51 2us 25 6us 0 1 0 210 fX 102us 51 2us 0 1 1 211 fX 204us 102us 1 0 0 213 fX 819us 409us 1 0 1 215 fX 3 27ms 1 63ms 1 1 0 217 fX 13 1ms 6 55ms 1 1 1 218 fX 26 2ms 13 1ms Note 1 To change the setting of the OSTS register you must change it before placing the MSTOP position of CLOCK Operating Stat...

Page 85: ... A LCD bus interface note Note The serial interface SPI0 1 afcan2 LCD bus interface is a BAT32G179 specific function Set the PER0 registers PER1 registers PER2 registers and PER2 registers via the 8 bit memory operation instructions PER3 register After generating a reset signal the value of these registers changes to 00H Figure 4 9 The format of Peripheral enable register 0 PER0 1 3 Address 400204...

Page 86: ...is in reset state 1 An input clock is provided Can read and write SFR used by the serial interface IICA0 SCI1EN Provides control of the input clock of the Universal Serial Communication Unit 1 0 Stop providing the input clock Cannot write SFR for Universal Serial Communication Unit 1 Universal Serial Communication Unit 1 is in reset state 1 An input clock is provided SFR can read and write to univ...

Page 87: ... 2 Address 4002081AH after reset 00H R W Symbol PER1 DACEN Provides control of the input clock of the D A converter 0 Stop providing the input clock Cannot write SFR used by D A converters The D A converter is in reset state 1 An input clock is provided Can read and write SFR used by D A converters TMBEN Provides control of the input clock of timer B 0 Stop providing the input clock Cannot write S...

Page 88: ...can run PWMOPEN PWM cut off circuit control of the input clock 0 Stop providing the input clock Cannot write SFR for PWM cut off circuits The PWM cut off circuit is in reset state 1 An input clock is provided Can read and write SFR used in PWM cut off circuits TMCEN Provides control of the input clock of Timer C 0 Stop providing the input clock SFR cannot be written to Timer C Timer C is in reset ...

Page 89: ...e serial interface IICA1 0 Stop providing the input clock Cannot write the serial interface IICA1 using the SFR Serial interface IICA1 is in reset state 1 An input clock is provided SFR can read and write serial interface IICA1 CAN1IN Provides control of the input clock of the CAN1 module 0 Stop providing the input clock Cannot write CAN1 using SFR CAN1 is in reset state 1 An input clock is provid...

Page 90: ... 0 Stop providing the input clock Cannot write SFR for serial interface SPI1 Serial interface SPI1 is in reset state 1 An input clock is provided Can read and write SFR for serial interface SPI1 Note The serial interface SPI0 1 afcan2 LCD bus interface is a BAT32G179 specific function so the BIT 5 7 of PER2 must be set to 1 b0 when BAT32G139 products Figure 4 12 The format of Peripheral enable reg...

Page 91: ...t of the mode control register OSMC Address 40020423H reset 00H R W SYMBOL 7 6 5 4 3 2 1 0 OSMC RTCLPC The settings in deep sleep mode and sleep mode where the CPU runs on the subsystem clock 0 Allows a subsystem clock to be provided for peripheral functions For peripheral functions that are allowed to operate please refer to Table 2 7 1 Table 2 7 3 1 Stop providing a subsystem clock for periphera...

Page 92: ...CODIV2 HOCODIV1 HOCODIV0 Selection of high speed internal oscillator clock frequency FRQSEL4 0 FRQSEL4 1 FRQSEL3 0 FRQSEL3 1 FRQSEL3 0 FRQSEL3 1 0 0 0 fIH 24MHz fIH 32MHz fIH 48MHz fHOCO 48MHz fIH 64MHz fHOCO 64MHz 0 0 1 fIH 12MHz fIH 16MHz fIH 24MHz fHOCO 48MHz fIH 16MHz fHOCO 64MHz 0 1 0 fIH 6MHz fIH 8MHz fIH 12MHz fHOCO 48MHz fIH 8MHz fHOCO 64MHz 0 1 1 fIH 3MHz fIH 4MHz fIH 3MHz fHOCO 48MHz fIH...

Page 93: ... the frequency changes In the event of a change in temperature and voltage at the VDD pin corrections need to be made before requiring accuracy of the frequency or periodically Figure 4 15 The format of the Trimming Register HIOTRM of the high speed internal oscillator Address 40021C00H reset value Note R W SYMBOL 7 6 5 4 3 2 1 0 HIOTRM HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High speed in...

Page 94: ...instructions After generating a reset signal the value of this register changes to 00H Figure 4 16 Format of subsystem clock selection registers SUBCKSEL Address 40020407H reset 00H R W SYMBOL 7 6 5 4 3 2 1 0 SUBCKSEL LOCOSEL Frequency selection for low speed internal oscillator clocks 0 Low speed internal oscillator clock frequency is 15K 1 Low speed internal oscillator clock frequency is 30K SEL...

Page 95: ... of the main system clock control register MCKC Address 40020C00H After reset 00H R W Note 1 SYMBOL 7 6 5 4 3 2 1 0 MCKC CKSTR The state of the high speed internal oscillator clock and PLL clock selection 0 Select high speed internal oscillator clock 1 Select the PLL clock PDIV1 PDIV0 Divider selection for the PLL clock 0 0 No Dividers 0 1 Divide by 2 1 0 Divide by 4 1 1 8 way CKSELR High speed in...

Page 96: ...in Figure Fig 4 18 Fig 4 1818 X1 oscillation circuit Vss X1 X2 Crystal oscilator or ceramic oscillator a Crystal or Ceramic oscilator b external clock EXCLK external clock Precautions are shown on the following page 4 4 2 XT1 oscillation circuit The XT1 oscillation circuit passes through a crystal resonator 32 768kHz TYP connecting the XT1 pin to the XT2 pin to oscillate When using the XT1 oscilla...

Page 97: ...n order to avoid the influence of the wiring capacitance etc the Fig 4 18418 Fig 4 19419 must be routed by the following method The wiring must be kept as short as possible Cannot cross with other signal lines and cannot approach the wiring through which large currents vary The capacitor grounding point of the oscillation circuit must always be the same as the VSS potential and the grounding patte...

Page 98: ...e is a power or ground graphic below the wiring of X1 and X2 Note In a multilayer board or double sided panel you cannot configure the power supply or ground graphics below the wiring area of the X1 pin X2 pin and resonator the dashed part of the figure The wiring cannot produce a capacitive component that affects the oscillation characteristics Note In the case of using a subsystem clock replace ...

Page 99: ...long grounding of oscilation circuit Point A B C has difference in electric potential high current high current g extracted signal Note that when the X2 and XT1 are routed in parallel the crosstalk noise of the X2 will be superimposed on the XT1 and cause malfunction Note In the case of using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively when reading and insert a series resisto...

Page 100: ...ck is used as a watchdog timer a real time clock a clock for a 15 bit interval timer and a clock for timer A as well as an external reference clock for the SysTick timer but cannot be used as a CPU clock When the bit4 WDTON of option byte 000C0H or bit4 WUTMMCK0 of the subsystem clock provides mode control register OSMC oscillates at a low speed internal oscillator when it is 1 When the watchdog t...

Page 101: ...ystem clock fMAIN High speed system clock fMX X1 clock fX External master system clock fEX High speed internal oscillator clock fIH Subsystem clock fSUB XT1 clock fXT External subsystem clock fEXS Low speed internal oscillator clock fIL CPU peripheral hardware clock fCLK After the BAT32G179 reset is released the CPU starts operating through the output of the high speed internal oscillator The oper...

Page 102: ...ge shown in the AC characteristics of the data sheet is reached the figure above is an example of when using an external reset If the reset is released the high speed internal oscillator automatically begins oscillating After the reset is released a voltage stabilization wait and reset process is performed and then the CPU starts running with a high speed internal oscillator clock The X1 clock or ...

Page 103: ... internal oscillator In addition the frequency can be changed by the frequency selection register HOCODIV of the high speed internal oscillator Setting of option bytes Address 000C2H Options 7 6 5 4 3 2 1 0 byte 000C2H FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of a high speed internal oscillator fHOCO fIH 1 1 0 0 0 64MHz 64MHz 1 0 0 0 0 48MHz 48MHz 0 1 0 0 0 32MHz 32MHz 0 0 0 0 0 24MHz 24M...

Page 104: ...FRQSEL3 0 FRQSEL3 1 FRQSEL3 0 FRQSEL3 1 0 0 0 fIH 24MHz fIH 32MHz fIH 48MHz fHOCO 48MHz fIH 64MHz fHOCO 64MHz 0 0 1 fIH 12MHz fIH 16MHz fIH 24MHz fHOCO 48MHz fIH 16MHz fHOCO 64MHz 0 1 0 fIH 6MHz fIH 8MHz fIH 12MHz fHOCO 48MHz fIH 8MHz fHOCO 64MHz 0 1 1 fIH 3MHz fIH 4MHz fIH 6MHz fHOCO 48MHz fIH 4MHz fHOCO 64MHz 1 0 0 Prohibit settings fIH 2MHz fIH 3MHz fHOCO 48MH fIH 2MHz fHOCO 64MHz 1 0 1 Prohibi...

Page 105: ...nd when fX is greater than or equal to 10MHz AMPH Bit set to 1 to make the X1 oscillation circuit run 7 6 5 4 3 2 1 0 CMC 2 The oscillation stabilization time of the X1 oscillation circuit when the deep sleep mode is deactivated through the OSTS register Example To wait at least 102 us through a 10MHz resonator it must be set to the following values 7 6 5 4 3 2 1 0 OSTS 3 Clear the MSTOP bit of th...

Page 106: ... subsystem clock the RTCPC bit must be set to 1 when the real time clock and the 15 bit interval timer are running at the sub system clock ultra low consumption current 7 6 5 4 3 2 1 0 OSMC 2 Place the OSCSELS position of the CMC register 1 so that the XT1 oscillation circuit runs 7 6 5 4 3 2 1 0 Cmc AMPHS0 bit and AMPHS1 bit Sets the oscillation mode of the XT1 oscillation circuit 3 Clear the XTS...

Page 107: ...rnal oscilator in Operation CPU high speed internal oscillator deep sleep mode CPU high speed internal oscillator sleep mode CPU XT1 oscillation EXCLKS input in Operation CPU XT1 oscillation EXCLKS input sleep mode CPU XT1 oscillation EXCLKS input in Operation CPU XT1 oscillation EXCLKS input sleep mode CPU X1 oscillation EXCLK input deep sleep mode A B H C D G F I X1 oscilation EXCLK input stop i...

Page 108: ... 1 1 Note 2 0 No confirmati on is required 1 Note 1 After the reset is released the control register CMC can only be written once through the 8 bit memory operation instruction 2 The oscillation settling time of the Oscillation Settling Time Selection Register OSTS must be set as follows The oscillation settling time of the State Register OSTC of the Expected Oscillation Settling Time Counter the ...

Page 109: ...of the Oscillation Settling Time Selection Register OSTS must be set as follows The oscillation settling time of the State Register OSTC of the Expected Oscillation Settling Time Counter the Oscillation Settling Time of the OSTS Register Settings Note The clock must be set after the supply voltage reaches the set clock operatable voltage refer to datasheet 5 The CPU shifts from high speed internal...

Page 110: ...e 7 The CPU shifts from high speed system clock operation C to secondary system clock operation D SFR registers are set in order Setting flag for the SFR register State transition CSC registers Wait for the oscillation accuracy to stabilize CKC registers XTSTOP CSS C D 0 required 1 Not required in subsystem clock operation 8 The CPU shifts from subsystem clock operation D to high speed internal os...

Page 111: ...ed system clock operation Note The oscillation settling time of the Oscillation Settling Time Selection Register OSTS must be set as follows The oscillation settling time of the State Register OSTC of the Expected Oscillation Settling Time Counter the Oscillation Settling Time of the OSTS Register Settings Note The clock must be set after the supply voltage reaches the set clock operatable voltage...

Page 112: ...nal oscillator clock operation B The CPU is transferred to deep sleep mode I during high speed system clock operation C Set Order State transition Content of configuration B M Stop it Peripheral features that do not run in deep sleep mode The SCR register bit2 SLEEPDEEP is set to 1 and the WFI instruction is executed C E X1 oscillates Set the OSTS register External clock Note Table 4 3of A I corre...

Page 113: ...XCLKS 1 XTSTOP 0 X1 clock High speed internal oscillator clock Allows high speed internal oscillator oscillation HIOSTOP 0 After a stable time of oscillation Can stop oscillation of X1 MSTOP 1 External master system clock Cannot be transferred XT1 clock The XT1 oscillates stably OSCSELS 1 EXCLKS 0 XTSTOP 0 After a stable time of oscillation Can stop oscillation of X1 MSTOP 1 External subsystem clo...

Page 114: ...et the external clock of the EXCLK pin input to be active and select the high speed system clock as the main system clock OSCSEL 1 EXCLK 1 MSTOP 0 MCS 1 External subsystem clock Cannot be transferred External subsystem clock High speed internal oscillator The high speed internal oscillator is oscillating and selects high speed internal The input of the external subsystem clock can be invalidated c...

Page 115: ...a high speed internal oscillator clock If you switch the CPU clock you also switch the peripheral hardware clock Table 4 5 time required to switch the main system clock Clock A Switch directions Clock B remark fIH fMX Refer to Table 4 6 fMAIN fSUB Refer to Table 4 7 Table 4 6 Maximum number of clocks required for IH fMX The setting value before switching The setting value after the switch MCM0 MCM...

Page 116: ... settings before clock oscillation stops clock Condition before clock stop external clock input is invalid Flag setting for SFR registers High speed internal oscillator clock MCS 1 or CLS 1 The CPU runs on a clock other than the high speed internal oscillator clock HIOSTOP 1 X1 clock MCS 0 or CLS 1 The CPU runs on a clock other than the high speed system clock MSTOP 1 External master system clock ...

Page 117: ...uency correction Interval action mode A mode that uses a timer clock end etc to perform high speed internal vibration frequency correction at intervals Clock accuracy adjustment function Correction time Correction period 31 2ms number of corrections 0 5 Note interrupt Interrupt when high speed internal frequency correction is complete when interrupt permission is open Note Correction time Varies d...

Page 118: ...nternal vibration frequency correction is completed 1 An interrupt occurs after the high speed internal oscillation frequency correction is complete FCST Note 2 High speed internal vibration frequency correction circuit action control status 0 High speed internal vibration frequency correction circuit action stop stop 1 High speed internal vibration frequency correction circuit action start action...

Page 119: ... 4 11High speed internal oscillator input frequency and correction period fHOCO MHz FRQSEL4 FRQSEL3 Note Correction Period ms 64 11 31 2 Frequency measurement phase frequency correction phase 48 10 32 01 24 00 Note FRQSEL4 FRQSEL3 is bit4 bit3 for option bytes0 0C2H During the frequency measurement phase of the correction period the frequency of the high speed internal oscillation is corrected acc...

Page 120: ...The correction value is 1 Count value is hours longer than expected Correction value 1 When the count value is within the expected value the correction value is maintained the high speed internal oscillation clock frequency correction ends When the FCIE bit of the HOCOFC register is set to 1 an interrupt is generated when the high speed internal oscillator clock frequency correction is completed I...

Page 121: ... value is within the expected value the correction value is maintained the high speed internal oscillation clock frequency correction ends When the FCIE bit of the HOCOFC register is set to 1 an interrupt is generated when the high speed internal oscillator clock frequency correction is completed In the interval mode the high speed internal oscillating clock frequency correction function repeats t...

Page 122: ... Action during reset Before entering deep sleep the high speed internal oscillating clock frequency correction function must be stopped Processing execution note CRCTL 40H Does the high speed internal frequency correction completion interrupt occur High speed internal frequency correction continuous action mode setting Allow high speed internal frequency correction completion interrupt CRCTL 41H A...

Page 123: ...curs the software settings need to be set again to enable the vibration stop detection action The vibration stop detection circuit determines the vibration stop time vibration stop judgment time is set by the OSDCCMP11 OSDCCMP0 of the vibration stop detection control register OSDC Oscillation stop determination time Internal low speed oscillation clock fIL period OSDCCMP11 OSDCCMP0 setting value 1...

Page 124: ...ation instructions to manipulate the SCMCTL registers Figure 4 30Format of the Vibration Stop Detection Control Register SCMCTL Address 0x40022200 After reset 0FFFH R W symbol 15 14 13 12 11 10 9 8 SCMCTL OSCDE 0 0 0 OSDCCMP11 8 symbol 7 6 5 4 3 2 1 0 SCMCTL OSDCCMP7 0 OSDCE Vibration stops detecting the action of the action 0 Vibration stop detection action stops 1 Vibration stop detection action...

Page 125: ...fsx MDSEL Vibration stops the action after detection 0 An interruption occurs after the vibration stop is detected 1 Vibration stops detecting and produces a reset Note When rewriting MDSEL and CKSEL the high 8 bit KEY of SCMMD must be written at the same time 0x3C For example after resetting the initial value of the SCMMD register is 0x00 and the CKSEL position is 1 by writing 0x3C01 to the SCMMD...

Page 126: ... clock fmx or the CPU clock is a PLL clock with the main system clock fmx as the PLL input and the main system clock fmx oscillation stop detection the CPU clock switches to the partition 8 fHOCO 8 of the internal high speed oscillation clock and when the CPU clock is a sub system clock fsx and there is a subsystem clock fsx vibration stop detection The CPU clock switches to the internal low speed...

Page 127: ...tion stop detection function Vibration stop detection circuit used with a watchdog timer Vibration stop detection which can be used under any of the following conditions When bit0 WDSTBYON of the option byte 00C0H bit4 WDTON is 1 and bit4 WUTMMCK0 of the OSMC register is 0 When bit4 WUTMMCK0 of the OSMC register is 1 ...

Page 128: ...are divider you need to set the DIVIDEND register DIVIDEND first and then the DIVISOR because a write to the divisor register automatically triggers the division calculation By querying the STATUS BIT of the BUZZ or by using an interrupt at the end of the calculation you can know when the settlement ended The calculation results can be read through the quotient QUOTIENT and remainder REMAINDER reg...

Page 129: ... calculation 31 30 29 28 27 26 25 24 DIVISOR 31 24 23 22 21 20 19 18 17 16 DIVISOR 23 16 15 14 13 12 11 10 9 8 DIVISOR 15 8 7 6 5 4 3 2 1 0 DIVISOR 7 0 5 3 3 Quotient After the division calculation is completed the register holds the quotient of the division calculation result whose value is a 32 bit signed integer 31 30 29 28 27 26 25 24 QUOTIENT 31 24 23 22 21 20 19 18 17 16 QUOTIENT 23 16 15 14...

Page 130: ...nd the BUSY flag 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved DIVBYZE RO BUSY 7 6 5 4 3 2 1 0 reserved DIVBYZERO Used to indicate the case of division by zero updated each time the divisor register is written 0 The divisor is not 0 1 The divisor is 0 BUSY Used to indicate the status of the division operation 0 Division is complete 1 The divisor o...

Page 131: ...th two general purpose timers Timer4 and Timer8 so m 0 1 2 The designator n later in this chapter represents the channel number in this chapter when m 0 n 0 3 m 1 n 0 7 and the presence or absence of timer input output pins for each channel varies depending on the product For details please refer to Chapter 2 Pin Functions 3 The following in this chapter are primarily described for 100 pin product...

Page 132: ...y divider with reference to 6 8 3 Measurement of input pulse interval refer to 6 8 4 Measurement of the high and low level width of the input signal reference 6 8 5 Delay counter reference 6 8 6 The Channel 1 and Channel 3 16 bit timers of Unit 0 can be used as two 8 bit timers high and low Channels 1 and 3 can be used as 8 bit timers as follows Interval timers high 8 bit and low 8 bit timers squa...

Page 133: ...n of the timer TOmn Comparision operation Action clock channel N timer output TOmn 3 External event counters The effective edges of the input signal of the timer input pin TImn are counted and if a specified number of times are reached can be used as an event counter that generates an interrupt Comparision operation channel N interrupt singnal INTTmn timer input TImn 4 Crossover function limited t...

Page 134: ...etection channel N timer input TImn 00H xxH capture start 7 Latency counters The effective edges of the input signal at the timer input pin TImn start counting and generate an interrupt after an arbitrary delay period Comparision operation edge detection channel N timer input TImn interrupt singnal INTTmn start Note 1 m unit number m 0 1 n channel number when m 0 n 0 3 m 1 n 0 7 2 The presence or ...

Page 135: ...width output timing sequence timer output TOmp interrupt singnal INTTmn 2 PWM Pulse Width Modulation output Pairing the two channels generates pulses with arbitrary set periods and duty cycles Comparision operation channel N master control Action clock Comparision operation channel P slave timer output TOmp duty cycle period interrupt singnal INTTmn 3 Multiple PWM Pulse Width Modulation outputs It...

Page 136: ...e input signal on the UART0 serial data input pin RxD0 starts counting and captures the count value on the rising edge to measure the low level width If the low level width is greater than or equal to a fixed value it is considered a wake up signal 2 Detection of interval segments After the wake up signal is detected the low level width is measured by starting the falling edge of the input signal ...

Page 137: ...nnel stop register m TTm Timer input selection register 0 TIS0 Timer output enable register m TOEm Timer output register m TOm Timer output level register m TOLm Timer output mode register m TOMm register for each channel Timer mode register mn TMRmn Timer status register mn TSRmn Input Switching Control Register ISC Noise filter enable registers 1 and 2 NFEN1 NFEN2 Port Mode Control Register PMCx...

Page 138: ...8 pins Unit 0 Channel 0 TI00 TO00 TI00 TO00 Channel 1 TI01 TO01 TI01 TO01 Channel 2 TI02 TO02 TI02 TO02 Channel 3 TI03 TO03 TI03 TO03 Unit 1 Channel 0 TI10 TO10 TI10 TO10 Channel 1 TI11 TO11 TI11 TO11 Channel 2 TI12 TO12 TI12 TO12 Channel 3 TI13 TO13 TI13 TO13 Unit 0 Channel 4 TI14 TO14 TI14 TO14 Channel 5 TI15 TO15 TI15 TO15 Channel 6 TI16 TO16 TI16 TO16 Channel 7 TI17 TO17 TI17 TO17 Remarks 1 Wh...

Page 139: ... TSOUT Timer input output selection register TIOS1 TI03 RXD0 Serial port input input switch control register ISC Channel 0 PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Timer clock selection register0 TPS0 pre scaler fCLK 215 fCLK 20 selector selector fCLK TM40EN peripheral enable register0 PER0 selector selector 2 2 4 4 Channel 1 Channel 2 Channel 3 CK03 CK02...

Page 140: ...H 0x1A0 TSR00L R 8 00H 0x1A2 TSR01 R 16 0000H 0x1A2 TSR01L R 8 00H 0x1A4 TSR02 R 16 0000H 0x1A4 TSR02L R 8 00H 0x1A6 TSR03 R 16 0000H 0x1A6 TSR03L R 8 00H 0x1B0 TE0 R 16 0000H 0x1B0 TE0L R 8 00H 0x1B2 TS0 R W 16 0000H 0x1B2 TS0L R W 8 00H 0x1B4 TT0 R W 16 0000H 0x1B4 TT0L R W 8 00H 0x1B6 TPS0 R W 16 0000H 0x1B8 TO0 R W 16 0000H 0x1B8 TO0L R W 8 00H 0x1BA TOE0 R W 16 0000H 0x1BA TOE0L R W 8 00H 0x1...

Page 141: ...H 0x18E TCR17 R 16 FFFFH 0x190 TMR10 R W 16 0000H 0x192 TMR11 R W 16 0000H 0x194 TMR12 R W 16 0000H 0x196 TMR13 R W 16 0000H 0x198 TMR14 R W 16 0000H 0x19A TMR15 R W 16 0000H 0x19C TMR16 R W 16 0000H 0x19E TMR17 R W 16 0000H 0x1A0 TSR10 R 16 0000H 0x1A0 TSR10L R 8 00H 0x1A2 TSR11 R 16 0000H 0x1A2 TSR11L R 8 00H 0x1A4 TSR12 R 16 0000H 0x1A4 TSR12L R 8 00H 0x1A6 TSR13 R 16 0000H 0x1A6 TSR13L R 8 00H...

Page 142: ...H 0x1B4 TT1 R W 16 0000H 0x1B4 TT1L R W 8 00H 0x1B6 TPS1 R W 16 0000H 0x1B8 TO1 R W 16 0000H 0x1B8 TO1L R W 8 00H 0x1BA TOE1 R W 16 0000H 0x1BA TOE1L R W 8 00H 0x1BC TOL1 R W 16 0000H 0x1BC TOL1L R W 8 00H 0x1BE TOM1 R W 16 0000H 0x1BE TOM1L R W 8 00H 0x318 TDR10 R W 16 0000H 0x31A TDR11 R W 16 0000H 0x364 TDR12 R W 16 0000H 0x366 TDR13 R W 16 0000H 0x368 TDR14 R W 16 0000H 0x36A TDR15 R W 16 0000...

Page 143: ... m 0 1 n channel number when m 0 n 0 3 m 1 n 0 7 The count value can be read by reading the timer count register mn TCRmn In the following cases the count value becomes FFFFH When a reset signal is generated When clearing the TM4EN TM8EN bit of peripheral enable register 0 PER0 End of count of dependent channels in PWM output mode The count of dependent channels ends in delay counting mode At the ...

Page 144: ...began Interval timer mode Decrement the count FFFFH The value at the time of stop Indefinite value Capture mode Increment the count 0000H The value at the time of stop Indefinite value Event counter pattern Decrement the count FFFFH The value at the time of stop Indefinite value Single count mode Decrement the count FFFFH The value at the time of stop Indefinite value FFFFH Capture single count mo...

Page 145: ...gister mn TDRmn n 0 2 4 5 6 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDRmn Figure 6 4 Timer data registers mn TDRmn n 1 3 TDR01H can support 8bit operation TDR01L can support 8bit operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDRmn i The case where the timer data register mn TDRmn is used as a comparison registerThe count is decremented from the setpoint of the TDRmn register and generates an int...

Page 146: ... register m TEm Timer channel start register m TSm Timer channel stop register m TTm Timer input and output selection register TIOS0 Timer output enable register m TOEm Timer output register m TOm Timer output level register m TOLm Timer output mode register m TOMm Input Switch Control Register ISC Noise filter enable register 1 NFEN1 Port Mode Control Register PMCxx Port Mode Register PMxx Port r...

Page 147: ...for reading and writing universal timer unit 0 TM8IN Control of the input clock of the universal timer unit 1 0 Stop providing the input clock SFR for universal timer unit 1 cannot be written Universal timer unit 1is reset 1 An input clock is provided SFR that can read and write for use in Universal Timer Unit 1 Note 1 To set the general purpose timer unit the following registers must first be set...

Page 148: ...PRSm00 PRSm03 bits can be rewritten when m 0 n 0 3 m 1 n 0 7 Channels that select CKm0 as the running clock CKSmn1 CKSmn0 0 0 are all in the stopped state TEmn 0 the case of PRSm10 PRSm13 bits can be rewritten when m 0 n 0 3 m 1 n 0 7 Channels selecting CKm2 as the operating clock CKSmn1 CKSmn0 0 1 are all in the stopped state TEmn 0 Cases where PRSm20 bits and PRSm21 bits can be rewritten n 1 3 C...

Page 149: ...7 81kHz 15 6kHz 39 1kHz 62 5kHz 1 0 1 0 fCLK 210 1 95kHz 3 91kHz 7 81kHz 19 5kHz 31 25kHz 1 0 1 1 fCLK 211 977Hz 1 95kHz 3 91kHz 9 77kHz 15 6kHz 1 1 0 0 fCLK 212 488Hz 977Hz 1 95kHz 4 88kHz 7 81kHz 1 1 0 1 fCLK 213 244Hz 488Hz 977Hz 2 44kHz 3 91kHz 1 1 1 0 fCLK 214 122Hz 244Hz 488Hz 1 22kHz 1 95kHz 1 1 1 1 fCLK 215 61 0Hz 122Hz 244Hz 610Hz 977Hz Note The universal timer unit TTm 0 100FH must be st...

Page 150: ...z 4 88kHz 7 81kHz 1 1 fCLK 214 122Hz 244Hz 488Hz 1 22kHz 1 95kHz Note The universal timer unit TTm 0 100FH must be stopped when changing the clock selected as fCLK changing the value of the system clock control register CKC Even when selecting the operating clock fMCK or the effective edge of the input signal of the TImn pin the general purpose timer unit needs to be stopped Note Bit15 14 11 10 mu...

Page 151: ...N n 2 4 6 CKSmn 1 CKSmn 0 0 CCSmn MASTER mn STSm n2 STSm n1 STSm n0 CISm n1 CISm n0 0 0 MDm n3 MDm n2 MDm n1 MDm n0 symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMRMN n 1 3 CKSmn 1 CKSmn 0 0 CCSmn SPLITmn STSm n2 STSm n1 STSm n0 CISm n1 CISm n0 0 0 MDm n3 MDm n2 MDm n1 MDm n0 symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMRMN n 0 5 7 CKSmn 1 CKSmn 0 0 CCSmn 0 Note 1 STSm n2 STSm n1 STSm n0 CISm n1...

Page 152: ...annel n 0 A slave channel that is used as a stand alone channel operation function or a multi channel linkage operation function 1 It is used as the main control channel of the multi channel linkage operation function Channels 2 4 6 can only be set as the main control channel MASTERmn 1 Channel 0 is fixed to 0 because channel 0 is the channel with the highest bit it is irrelevant to the setting of...

Page 153: ...8 7 6 5 4 3 2 1 0 RMRMN n 0 5 7 CKSmn 1 CKSmn 0 0 CCSmn 0 Note 1 STSm n2 STSm n1 STSm n0 CISm n1 CISm n0 0 0 MDm n3 MDm n2 MDm n1 MDm n0 CISmn1 CISmn0 Effective edge selection for the TImn pin 0 0 Falling edge 0 1 Rising edge 1 0 Bilateral edges when measuring low level widths Start Trigger Falling Edge Capture Trigger Rising Edge 1 1 Bilateral edges when measuring high level width Start trigger R...

Page 154: ...nt the count Other than the above Disable settings The operation of each mode varies depending on the MDmn0 bit see the table below Operating mode MDmn3 MDmn1 bit setting refer to table above MD mn0 Start count and interrupt settings Interval timer mode 0 0 0 capture mode 0 1 0 0 No timer interrupt is generated at the start of counting nor does the output of the timer change 1 A timer interrupt is...

Page 155: ...alue of the TSRmn register changes to 0000H Figure 6 12 timer status register mn TSRmn symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF OVF Counter overflow status for channel n 0 No overflow occurred 1 Overflow occurs If the OVF bit is 1 clear this flag OVF 0 just when the next count does not overflow and the count value is captured Note m unit number m 0 1 n c...

Page 156: ...f the TEm register changes to 0000H Figure 6 13 timer channels Enabled status register m TEm symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEm 0 0 0 0 TEHm 3 0 TEHm 1 0 0 0 0 0 TEm 3 TEm 2 TEm 1 TEm 0 m 0 symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEm 0 0 0 0 0 0 0 0 TEm 7 TEm 6 TEm 5 TEm 4 TEm 3 TEm 2 TEm 1 TEm 0 m 1 TEHm3 Channel 3 is an indication of the high 8 bit timer when the operation o...

Page 157: ... the counting Enabled state it enters interval timer mode see Table 6 6 of Start Timing of the Counter 6 5 2 TSHm1 The operation of the high 8 bit timer when Channel 1 is in 8 bit timer mode enable start triggering 0 No triggering 1 Place TEHm1 at position 1 and enter the Count Enabled state If the count of TCRm1 registers is started in the counting Enabled state it enters interval timer mode see ...

Page 158: ... channel stop register m TTm symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTm 0 0 0 0 TTHm 3 0 TTHm 1 0 0 0 0 0 TTm3 TTm2 TTm1 TTm0 m 0 symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTm 0 0 0 0 0 0 0 0 TTm7 TTm6 TTm5 TTm4 TTm3 TTm2 TTm1 TTm0 m 1 TTHm3 The operation of the high 8 bit timer is triggered when Channel 3 is in 8 bit timer mode 0 No triggering 1 Clear the TEHm3 bit to 0 and enter the c...

Page 159: ...hibited TIS04 Channel 0 uses the choice of timer input 0 Input signal selected by TIS07 TIS05 1 ElC s event input signal TOS03 Enable of the timer output of channel 2 0 Output is Enabled 1 Disable output output fixed to 0 TIS02 TIS01 TIS00 Channel 1 uses the choice of timer inputs 0 0 0 The input signal of the timer input pin TI01 0 0 1 Event input signal for EVENTC 0 1 0 The input signal of the t...

Page 160: ...n instruction After generating a reset signal the value of the TOEm register changes to 0000H Figure 6 17 timer outputs Enabled register m TOEm symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOEm 0 0 0 0 0 0 0 0 0 0 0 0 TOE m3 TOE m2 TOE m1 TOE m0 m 0 symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOEm 0 0 0 0 0 0 0 0 TOE m7 TOE m6 TOE m5 TOE m4 TOE m3 TOE m2 TOE m1 TOE m0 m 1 TOEmn Allow disable of t...

Page 161: ...in as a port function the corresponding TOmn position must be 0 The TOm register is set by the 16 bit memory operation instructions User can set the lower 8 bits of the TOm register with TOmL and through the 8 bit memory operation instruction After generating a reset signal the value of the TOm register changes to 0000H Figure 6 18 timer output register m TOm symbol 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 162: ...m register with TOLmL and through the 8 bit memory operation instruction After generating a reset signal the value of the TOLm register changes to 0000H Figure 6 19 Timer output level register m TOLm symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dust 0 0 0 0 0 0 0 0 0 0 0 0 TOL m3 TOL m2 TOL m1 0 m 0 symb ol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dust 0 0 0 0 0 0 0 0 Dus t7 DU ST6 Dus t5 Dus t4 TOL...

Page 163: ...ration instruction After generating a reset signal the value of the TOMm register changes to 0000H Figure 6 20 timer output mode register m TOMm symbo l 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOMm 0 0 0 0 0 0 0 0 0 0 0 0 TOM m3 TOM m2 TOM m1 0 m 0 symbo l 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOMm 0 0 0 0 0 0 0 0 TOM m7 TOM m6 TOM m5 TOM m4 TOM m3 TOM m2 TOM m1 0 m 1 TOMmn Control of the timer outp...

Page 164: ...0H R W symbol 7 6 5 4 3 2 1 0 ISC SYESE00 0 0 0 0 0 ISC1 ISC0 SSIE00 The SSI00 pin input setting for channel 0 in the slave mode of the CSI00 communication 0 The SSI00 pin input is invalid 1 The SSI00 pin input is valid ISC1 Input switching of channel 3 of the universal timer unit 0 0 Use the input signal from the TI03 pin as the input to the timer usually operating 1 Use the input signal from the...

Page 165: ...oise filter allowable register 1 NFEN1 Address 0x40040471 After reset 00H R W symbol 7 6 5 4 3 2 1 0 NFEN1 0 0 0 0 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Address 0x40040472 After reset 00H R W symbol 7 6 5 4 3 2 1 0 NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10 TNFEN03 the usage or not of input signal noise filters at the TI03 pin or RxD0 pin Note 0 Noise filter OFF 1 Noise filter...

Page 166: ...sing the multiplex port of the timer output pin as the output of the timer the bit of the port mode control register PMCxx the bit of the port mode register PMxx and the position of the port register Pxx 0 must be used for each port Example When P01 TO00 is used as a timer output Place the port mode control register 0 at PMC01 position 0 Place the PORT mode register 0 at the PM01 position 0 Place ...

Page 167: ...mn TMRmn values need to be the same setpoint 7 The master channel can pass intTMmn interrupt start software trigger and count clock to the low channel 8 Slave channels can use the master channel s INTMmn interrupt start software trigger and count clock as the source clock but cannot pass their own INTMmn interrupt start software trigger and count clock to the low channel 9 The master channel canno...

Page 168: ...ster control Channel 3 Slave CK01 Channel Group 1 multi channel linked operation function Channel Group 2 multi channel linked operation function Example 2 Timer4 Channel 0 Master control Channel 1 independent channel operation function CK00 Channel 3 independent channel operation function Channel 2 Slave CK00 Channel Group 1 multi channel linked operation function CK01 ...

Page 169: ...ate If the count of TCRm3 registers is started in the counting Enabled state it enters interval timer mode see Table 6 6 of Start Timing of the Counter 6 5 2 TSHm1 The operation of the high 8 bit timer when Channel 1 is in 8 bit timer mode enable start triggering 0 No triggering 1 Place teem1 at position 1 and enter the Count Enabled state If the count of TCRm1 registers is started in the counting...

Page 170: ...er depends on the setting of the CKSmn1 bit and CKSmn0 bits of the low TMRmn register 6 For high 8 bit timers the channel operation is started by operating the TSHm1 TSHm3 bits and the channel operation is stopped by operating the TTHm1 TTHm3 bits The status of the channel can be confirmed by tehm1 TEHm3 bits 7 The operation of the low 8 bit timer depends on the setting of the TMRmn register and t...

Page 171: ...or the operating clock fMCK Depending on the setting of the timer clock select register m TPSm the count clock fTCLK is fCLK fCLK 215 However when the division of fCLK is selected the clock selected by the TPSm register is a signal that starts with only 1 fCLK cycle high starting on the rising edge When fCLK is selected it is fixed to high To achieve synchronization with the fCLK the timer count r...

Page 172: ...f the input signal at the TImn pin Fig 6 25 count clock fTCLK CCSmn 1 without the use of a noise filter edge detection edge detection fCLK fMCK TSmn Write TEmn Timn input sample waveform rising edge detection singal fTCLK Start the operation of the timer by placing the TSmn position bit and wait for a valid edge of the TImn input The rising edge of the TImn input is sampled by fMCK The rising edge...

Page 173: ... 3 2 Run of the event counter pattern Capture mode No action is taken from the time it is detected and triggered until the counting clock is generated 0000H is loaded into the TCRmn register by the first counting clock and counted incrementally by subsequent counting clocks refer to the operation of 6 5 3 3 capture mode interval measurement of input pulses Single count mode By writing 1 to the TSm...

Page 174: ...llowing the first counting clock after running and start counting in interval timer mode 5 If the TCRmn register is decremented to 0000H the INTMmn is generated by the next count clock fMCK and the timer data register mn is generated The value of TDRmn continues counting after loading into the TCRmn register Figure 6 26 Runtime Sequence Interval Timer Mode when MDmn0 1 INTTMmn TDRmn TCRmn start tr...

Page 175: ...n TDRmn into the TCRmn register while both the TSmn bit and the TEmn bit become 1 and start counting 4 Thereafter at the effective edge of the TImn input the value of the TCRmn register is counted down by counting the clock Figure 6 27 Runtime Sequence Event Counter Pattern TSmn write TImn input counting clock start trigger detection singal TCR mn initial value edge detection edge detection Note T...

Page 176: ...starting at 0000H 5 If a valid edge of the next TImn input is detected the value of the TCRmn register is captured to the TDRmn register and an INTTmn interrupt is generated Figure 6 28 Runtime Sequence Capture Mode Interval Measurement of Input Pulses TSmn write TImn input rising edge start trigger detection singal TCR mn initial value when MDmn0 1 edge detection edge detection note 0001note Note...

Page 177: ...ated 3 Detect the rising edge of the TImn input 4 Load the value of the TDRmn register m into the TCRmn register after generating the start trigger signal and start counting 5 When the TCRmn register decreases the count to 0000H an INTTMmn interrupt is generated and the value of the TCRmn register becomes FFFFH stopping the count Figure 6 29 Runtime Sequence Single Count Mode TSmn write TImn input...

Page 178: ...r generating the start trigger signal and start counting 5 If the falling edge of the TImn input is detected the value of the TCRmn register is captured to the TDRmn register and an INTTmn interrupt is generated Figure 6 30 Runtime Sequence Capture Single Count Mode Measurement of High Level Width TSmn write TImn input rising edge falling edge start trigger detection singal initial value edge dete...

Page 179: ...TTMmn repositionINTTMmp Position When both INTMmn and INTMmp 0 of the output of the PWM output are generated at the same time the intTMmp reset signal is preferentially shielded INTTMmn assertion signal In a state that enable the timer output TOEmn 1 in which the intTMmn master channel timer interrupt and INTMmp slave channel timer interrupt are passed to the TOm registers The write operation of t...

Page 180: ...ndom value FFFFH after reset 1 Set the operating mode of the timer output TOMmn bits 0 master channel output mode 1 slave channel output mode TOLmn bits 0 positive logic output 1 negative logic output 2 Set the timer output signal to the initial state by setting the timer output register m TOm 3 Write 1 to the TOEmn bit allowing the timer output it is forbidden to write the TOm register 4 Set the ...

Page 181: ... Unit number m 0 1 n Channel number when m 0 n 0 3 m 1 n 0 7 2 The initial level of the TOmn pin and the output level after the timer starts running Write the timer output register m TOm before allowing the port output and in the state where the timer output TOEmn 0 is disabled and when the timer output Enabled state TOEmn 1 is set after changing the initial level The TOmn pin output level changes...

Page 182: ... m TOLm during timer operation If you change the setting of the TOLm register during timer operation the setting is valid when the TOmn pin change condition is generated The output level of the TOmn pin cannot be changed by overwriting the TOLm registers When the TOMmn bit is 1 the run when changing the value of the TOLm register in the timer run TEmn 1 is as follows Figure 6 35 When changing the ...

Page 183: ...es precedence The position reset operation state when setting the master slave channel according to the following method is shown in Figure 6 35 Main control channel TOEmn 1 TOMmn 0 TOLmn 0 Slave channels TOEmp 1 TOMmp 1 TOLmp 0 Figure 6 36 Assert Reset Timing Operation Status 1 Basic runtime order master control channel slave channel internal reset signal Tomn Pin TOmn swap internal reset signal ...

Page 184: ... 1 clock cycle internal reset signal internal reset signal Tomp Pin TOmp Set reset Set reset proritized reset proritized reset INTTMmp INTTMmn fTCLK TCRmp Note 1 Internal reset signal Reset alternate signal at the TOmn pin Internal position signal The position signal of the TOmn pin 2 m Unit number m 0 1 n channel number m 0 n 0 3 m 1 n 0 7 main control channel n 0 2 4 6 p Slave channel number n 0...

Page 185: ...he TO0n bit Before writing TO0 TOE0 The data to write 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 After writing TO0 Only TOmn bits with TOEmn bits as 0 can be written ignoring write operations for TOmn bits with TOEmn bits as 1 TOmn channel output with TOEmn bit 1 is not affected by write operations even the write TOmn bit is ignored and output changes caused by timer operation are normal Figure 6 38 state of...

Page 186: ...ontrolled An example of operation when set to interval timer mode TOEmn 1 TOMmn 0 is shown below Figure 6 39 An example of a timer interrupt and a TOmn output when counting starts a The case where the MDmn0 bit is 1 TCRmn TEmn INTTMmn TOmn Start counting b The case where the MDmn0 bit is 0 TCRmn TEmn INTTMmn TOmn Start counting When the MDmn0 bit is 1 the output timer interrupt INTTMmn is output a...

Page 187: ...ection Timer control circuit 6 7 2 Noise filters When the noise filter is invalid synchronization is performed only by the operating clock fMCK of channel n When the noise filter is active the two clocks are detected to be consistent after synchronization through the operating clock fMCK of channel n In the case of a noise filter ON or OFF at the TM4mn input pin the waveform after passing through ...

Page 188: ...ggering 1 When the noise filter is OFF If the timer mode register mn TMRmn is bit12 CCSmn bit9 STSmn1 and Bit8 STSmn0 will be any bit in a state where it is all 0 and it must pass through at least 2 operating clocks f MCK After the cycle the timer channel will be run to start the operation of the register TSm to enable trigger setting 2 When the noise filter is ON If the timer mode register mn TMR...

Page 189: ...er m TSm pass the first A counting clock loads the value of the timer data register mn TDRmn into the TCRmn register At this point if the MDmn0 bit of the timer mode register n TMRmn is 0 intTMmn is not output and TOmn also does not have alternating outputs If the MDmn0 bit of the TMRmn register is 1 intTMmn is output and TOmn is alternately output The TCRmn register then decrements the count thro...

Page 190: ...circuit interrupt control circuit Tomn Pin interrupt singal Note Clocks can be selected from CKm0 CKm1 CKm2 and CKm3 on channel 1 and 3 Figure 6 42 basic timing example of running as an interval timer square wave output MDmn0 1 Note 1 m unit number m 0 1 n channel number when m 0 n 0 3 m 1 n 0 7 2 TSmn The bitn of the timer channel start register m TSm TEmn The timer channel enable bitn of the sta...

Page 191: ...t Channel operation SPLITmn bit configuration Channel 1 3 0 16 bit Timer 1 8 bit Timer Count clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n 01B select CKm2 as operational clock of Channel 1 3 only Channle 1 3 can select the value 11B select CKm3 as operational clock...

Page 192: ...TSHm1 TSHm3 bit is the trigger bit The TEmn TEHm1 THEm3 bit becomes 1 and starts counting Load the value of the TDRmn register into the timer count register mn TCRmn When the MDmn 0 bit of the TMRmn register is 1 INTTMmn is generated and TOmn is output alternately Running You can change the settings of the TDRmn register at will Can read TCRmn register at any time TSRmn register cannot be used Can...

Page 193: ...g a valid edge of the input of the TImn pin If TCRmn becomes 0000H the value of the TDRmn register is loaded again and intTMmn is output After that the same run continues Because the TOmn pin outputs an irregular waveform based on an external event the timer output must be 0 at the TOEmn position of the enable register m TOEm to stop the output The TDRmn register can be overwritten at any time and...

Page 194: ...LITmn bit configuration Channel 1 3 0 16 bit Timer 1 8 bit Timer Count clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n 01B select CKm2 as operational clock of Channel 1 3 only Channle 1 3 can select the value 11B select CKm3 as operational clock of Channel 1 3 only C...

Page 195: ...ion of the Power Start Run Position TSmn 1 The TSmn bit is a trigger bit and is automatically returned to 0 The TEmn bit becomes 1 and starts counting The value of the TDRmn register is loaded into the timer count register mn TCRmn and enters the detection waiting state of the TImn pin input edge Running You can change the settings of the TDRmn register at will Can read TCRmn register at any time ...

Page 196: ... effective edges of the TImn pin input If the TCRmn becomes 0000H the TOmn is output alternately At the same time load the value of the TDRmn register into the TCRmn register and continue counting If the two sided edge of the TImn pin input is selected for detection the duty cycle error of the input clock affects the divider clock period of the TOmn output The clock cycle of the TOmn output contai...

Page 197: ... trigger selection 000B only select software to start trigger Count clock selection 1 Select TI00 pin output valid edge operational clock fMCK selection 00B select CK00 as operational clock of Channel 0 10B select CK01 as operational clock of channel 1 operation configuration when start counting 0 when start counting not to generate INTTMmn and do not generate inverted Phase Timer output 1 when st...

Page 198: ...0 bit is trigger bit thus automatically return to 0 TE00 bit turns to 1 and start counting Load TDR00 register value into Timer count register 00 TCR00 When MD000 bit of TMR00 register turns into 1 generate INTTM00 and TO00 swaps output in operation can modify any TDR00 register configuration value Can read TCR00 register anytime Do not use TSR00 register Can modify TO0 register and TOE0 register ...

Page 199: ... the TCRmn register is cleared 0000H then output INTMmn At this point if the counter overflows the OVF position of the timer status register mn TSRmn is 1 If the counter does not overflow the OVF bit is cleared After that the same run continues While the count value is captured to the TDRmn register the OVF bit of the TSRmn register is updated according to whether there is an overflow during the m...

Page 200: ...dependent Channel operation SPLITmn bit configuration Channel 1 3 0 16 bit Timer Count clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n 01B select CKm2 as operational clock of Channel 1 3 only Channle 1 3 can select the value 11B select CKm3 as operational clock of Ch...

Page 201: ...on can only modify configure value of CISmn1 bit and CISmn0 bit of TMRmn register Can read TDRmn register anytime Can read TCRmn register aanytime Can read TSRmn register anytime Forbidden modifying TOMmn bit TOLmn bit TOmn bit and TOEmn bit configuration Counter TCRmn start incremental counting from 0000H if detecting TImn pin input valid edge or TSmn bit set to 1 then transfer capture counting v...

Page 202: ...easuring the high level width is measured the intTMmn is output at the same time that the count value is passed to the timer data register mn TDRmn At this point if the counter overflows the OVF position bit of the timer status register mn TSRmn is placed If the counter does not overflow the OVF bit is cleared The value of the TCRmn register changes to Value passed to TDRmn register 1 and stops co...

Page 203: ...l width measurements TSmn TEmn TImn TCRmn TDRmn INTTMmn OVF Note 1 m unit number m 0 1 n channel number m 0 n 0 3 m 1 n 0 7 2 TSmn Bitn of the timer channel start register m TSm Temn The bit n of the timer channel enable the status register m TEm TImn The TImn pin input signal TCRmn Timer count register mn TCRmn TDRmn Timer data register mn TDRmn OVF Bit0 of the timer status register mn TSRmn ...

Page 204: ...ct operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n 01B select CKm2 as operational clock of Channel 1 3 only Channle 1 3 can select the value 11B select CKm3 as operational clock of Channel 1 3 only Channle 1 3 can select the value Timn Pin input edge selection 10B selection both edges measur...

Page 205: ...r mn TCRmn to 0000H and start decremental counting in operation can modify any TDRmn register configuration value Can read TCRmn register anytime Do not use TSRmn register Forbidden modifying TMRmn register TOMmn bit and TOLmn bit Tomn and T0Emn bit configuration value while detecting TImn pin start edge Counter TCRmn start incremental counting from 0000H if detecting TImn pin input capture edge t...

Page 206: ...lid edge detection wait state for the TImn pin By detecting the valid edge of the TImn pin input the operation of the TCRmn register begins and the value of the timer data register mn TDRmn is loaded The TCRmn register decrements the count from the value of the loaded TDRmn register by counting the clock If TCRmn becomes 0000H INTMmn is output and counts are stopped before a valid edge of the next...

Page 207: ...al clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n 01B select CKm2 as operational clock of Channel 1 3 only Channle 1 3 can select the value 11B select CKm3 as operational clock of Channel 1 3 only Channle 1 3 can select the value Timn Pin input edge selection 00B Detect falling edge 01B Detect rising edge 10B Detect both edg...

Page 208: ...automatically return to 0 TEmn bit turns into 1 and enter into start trigger detect Timn pin input valid edge or set TSmn bit to 1 detection waiting state start decremental counting while detecting next start trigger Detect TImn pin input valid edge set TSmn bit to 1 via software load TDRmn register value into Timer counting register mn TCRmn in operation can modify any TDRmn register configuratio...

Page 209: ...nd loads the value of the TDRmp register The TCRmp register decrements the count from the loaded TDRmp register value by counting the clock If the count value changes to 0000H intTMmp is output and the count is stopped before the next start trigger INTMmn of the master channel is detected After generating INTMmn from the master channel and passing through a count clock the output level of TOmp bec...

Page 210: ...ng mode slave channel operational clock clock selection trigger selection clock selection trigger selection Timer count register mn TCRmn Timer data register mn TDRmn Timer count register mp TCRmp Timer data register mp TDRmp interrupt control circuit output control circuit interrupt control circuit TOmp Pin interrupt signal INTTMmp interrupt signal INTTMmn Note m Unit number m 0 1 n Master channe...

Page 211: ... b a 2 b master control channel slave channel Note 1 m Unit number m 0 1 n Master channel number n 0 2 4 6 p Slave channel number m 0Time n p 3 m 1Time n p 7 2 TSmn TSmp the bit n p of the timer channel start register m TSm TEmn TEmp The timer channel enable bitn p of the status register m TEm TImn TImp Input signals for the TImn pin and TImp pin TCRmn TCRmp Timer count registers mn mp TCRmn TCRmp...

Page 212: ...control channel counting clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n TImn Pin input edge selection 00B Detect falling edge 01B Detect rising edge 10B Detect both edges 11B reserved b The timer output register m TOm bit n TOm TOmn 0 0 Outputs 0 by TOmn c The timer...

Page 213: ...elect operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel p 10B select CKm1 as operational clock of Channel p same as master control channel configuration TImp Pin input edge selection 00B set to 00 since not used b The timer output register m TOm bit p TOm TOmp 1 0 0 Output 0 by TOmp 1 Output 1 by TOmp c The timer output enable register m TOEm b...

Page 214: ...ode registers mn mp of 2 channels TMRmn TMRmp confirm channel operation mode Set master control channel Timer data register mn TDRmn configure output delay time and set slave channel TDRmp register pulse width channel in operation stopped state providing clock consume portion of power slave channel configuration set TOMmp bit of timer output mode register m TOMm to 1 slave channel output mode Conf...

Page 215: ...l counting If TCRmn counts till 0000H then generating INTTMmn and stop counting before next Timn pin input Slave channel use INTTMmn of master channel as trigger will load TDRmp register value into TCRmp regiter and counter start decremental counting 1 counting clock cycle after master chanel outputs INTTMmn it sets T0mp otuput voltage to valid voltage level Then if TCRmp count reaches 0000H then ...

Page 216: ...oaded into the TCRmp register and counted down until 0000H When 0000H is counted INTMmp is output and waits for the next start to trigger INTMmn of the master channel When used as a PWM function the slave channel counts down to the duty cycle of the PWM output TOmp during the count until 0000H After generating INTMmn from the master channel and passing 1 clock the PWM output TOmp becomes the effec...

Page 217: ...ve channel clock selection trigger selection clock selection trigger selection Timer count register mn TCRmn Timer data register mn TDRmn Timer count register mp TCRmp Timer data register mp TDRmp interrupt control circuit output control circuit interrupt control circuit TOmp Pin interrupt signal INTTMmp interrupt signal INTTMmn Note m Unit number m 0 1 n Master channel number n 0 2 4 6 p Slave ch...

Page 218: ...1 c a 1 b 1 master control channel slave channel a b a c d c d Remarks 1 m Unit number m 0 1 n Master channel number n 0 2 4 6 p Slave channel number m 0Time n p 3 m 1Time n p 7 2 TSmn TSmp the timer channel starts the bitn p of the register m TSm TEmn TEmp The timer channel enable bitn p of the status register m TEm TCRmn TCRmp Timer count registers mn mp TCRmn TCRmp TDRmn TDRmp timer data regist...

Page 219: ...onfiguration Channel 2 1 master control channel counting clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n Timn Pin input edge selection 00B set to 00B since not used b The timer output register m TOm bit n TOm TOmn 0 0 Output 0 by TOmn c The timer output enable regist...

Page 220: ...onal clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel p 10B select CKm1 as operational clock of Channel p same as master control channel configuration Timp Pin input edge selection 00B set to 00B since not used b The timer output register m TOm bit p TOm TOmp 1 0 0 Output 0 by TOmp 1 Output 1 by TOmp c The timer output enable register m TOEm bit p TOEm TO...

Page 221: ...interal period value of Timer data register mn TDRmn of master control channel and configure duty cycle of slave channel TDRmp channel in operation stopped state providing clock consume portion of power slave channel configuration set TOMmp bit of timer output mode register m TOMm to 1 slave channel output mode Configure TOLmp bit Configure TOmp bit and confirm TOmp otuput initial voltage Set TOEm...

Page 222: ...egister value into TCRmp regiter and counter start decremental counting 1 counting clock cycle after master chanel outputs INTTMmn it sets T0mp otuput voltage to valid voltage level Then if TCRmp count reaches 0000H then set T0mp output voltage set to invalid votlage levle then stoop counting Thereafter the process repeats set TTmn bit master and TTmp bit slave to 1 Because TTmn bit and TTmp bit a...

Page 223: ...the INTMmn of the master channel the value of the TDRmq register is loaded into the TCRmq register and the count is decremented If TCRmq becomes 0000H INTMmq is output and counts are stopped before the input next starts triggering INTMmn of the master channel After generating INTMmn from the master channel and going through a count clock the output level of TOmq becomes effective if TCRmq becomes ...

Page 224: ...gger selection clock selection trigger selection Timer count register mn TCRmn Timer data register mn TDRmn Timer count register mp TCRmp Timer data register mp TDRmp interrupt control circuit output control circuit interrupt control circuit TOmp Pin interrupt signal INTTMmn interrupt signal INTTMmp Timer count register mq TCRmq Timer data register mq TDRmq output control circuit interrupt control...

Page 225: ...PWM output functions in the case of outputting two PWMs TSmn TEmn TCRmn FFFFH 0000H a TDRmn TOmn INTTMmn TSmp TEmp TCRmp FFFFH 0000H TDRmp INTTMmp TOmp a 1 c a 1 b 1 master control channel slave channel 1 a b a c d c d d TSmq TEmq TCRmq FFFFH 0000H TDRmq INTTMmq TOmq a 1 e a 1 b 1 slave channel 2 a e f e f f Note 1 m unit number m 0 1 n master channel number n 0 2 4 ...

Page 226: ...r m 1Time n p q 7 p和qis greater thanninteger 2 TSmn TSmp TSmq timer channel start register m TSm of bitn p q TEmn TEmp TEmq Timer channels enable bitn p and bitn of the status register m TEm q TCRmn TCRmp TCRmq Timer count registers mn mp mq TCRmn TCRmp TCRmq TDRmn TDRmp TDRmq Timer data registers mn mp mq TDRmn TDRmp TDRmq TOmn TOmp TOmq Output signals from the TOmn TOmp TOmq pins ...

Page 227: ...1 master control channel counting clock selection 0 Select operational clock fMCK operational clock fMCK selection 00B select CKm0 as operational clock of Channel n 10B select CKm1 as operational clock of Channel n Timn Pin input edge selection 00B set to 00B since not used b The timer output register m TOm bit n TOm TOmn 0 0 Outputs 0 by TOmn c The timer output enable register m TOEm bit n TOEm T...

Page 228: ...me as master control channel configuration Timp and TImq Pin input edge selection 00B set to 00B since not used CKSmp1 1 0 CKSmp0 0 0 CCSmp 0 M S 注 0 STSmp2 1 STSmp1 0 STSmp0 0 CISmp1 0 CISmp0 0 0 0 MDmp3 1 MDmp2 0 MDmp1 0 MDmp0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 TMRmp b The timer output register m TOm bit q bit p TOm TOmq 1 0 TOmp 1 0 0 Output 0 by TOmp and TOmq 1 Output 1 by TOmp and TOmq c...

Page 229: ...data register mn TDRmn of master control channel and configure duty cycle of slave channel TDRmp channel in operation stopped state providing clock consume portion of power slave channel configuration set TOMmp bit and TOLmq bit of timer output mode register m TOMm to 1 slave channel output mode Configure TOLmp and Tomq bit to 0 Configure TOmp bit and Tomq bit confirm TOmp and Tomq otuput initial ...

Page 230: ...utput voltage set to invalid votlage levle then stoop counting Slave channel 2 use INTTMmn of master channel as trigger will load TDRmq register value into TCRmq regiter and counter start decremental counting 1 counting clock cycle after master chanel outputs INTTMmn it sets T0mq otuput voltage to valid voltage level Then if TCRmq count reaches 0000H then set T0mq output voltage set to invalid vot...

Page 231: ...10 1 Considerations when using timer outputs Depending on the product pins assigned the timer output function may also be assigned to the output of other multiplexing functions When using the timer output in this case the output of the other multiplexing function needs to be set at the initial value For details please refer to Chapter 2 Pin Functions ...

Page 232: ...imer mode Count the count sources Pulse output mode The counting source is counted and a pulse with opposite polarity is output when the timer underflow occurs Event counter pattern Count external events It can also be operated in deep sleep mode Pulse width measurement mode Measures the pulse width of the external input Pulse period measurement mode Measures the pulse period of the external input...

Page 233: ...data bus 16 bit reload register underflow singal TEDGPL TEDGSEL TEDGSEL 1 TEDGSEL 0 000B 001B 011B 100B 101B 110B 00B 01B 10B 00B 01B 10B 11B RCCPDEL1 RCCPSEL0 01B 10B 11B TCK2 TCK0 Note 1 To select fIL as the counting source the subsystem clock must be supplied with the mode control register OSMC at WUTMMCK0 position 1 However when f SUB is selected as the counting source for the real time clock ...

Page 234: ...r A counts register 0 note TA0 Timer A controls register 0 TACR0 Timer AI O controls register 0 TAIOC0 Timer A mode register 0 TAMR0 Timer A event pin selects register 0 TAISR0 Port register x Px Port mode register x PMx Note When accessing the TA0 register the CPU does not enter the processing of the next instruction but is in the waiting state of CPU processing Therefore when this wait occurs th...

Page 235: ...his register changes to 00H Figure 7 2 the format of peripheral enable register 1 PER1 Address 4002081AH after reset 00HR W symbol PER1 TMAEN Provides control of the input clock of timer A 0 Stop providing the input clock Cannot write SFR for timer A Timer A is reset 1 An input clock is provided Can read and write the SFR used by timer A Note 1 To set timer A you must first place the TMAEN positio...

Page 236: ...mat of the mode control register OSMC provides for the sub system clock Address 40020423H after reset 00HR W Symbol 76543210 OSMC WUTMMCK0 Choice of real time clock 1 5 bit interval timer operating clock fRTC and timer A operating clock 0 Subsystem clock fSUB The secondary system clock is a real time clock and a 1 5 bit interval timer for the operating clock The low speed internal oscillator canno...

Page 237: ...nd the count value becomes FFFFH 2 If the setting value of the TCK2 TCK0 bit of the TAMR0 register is not 001B fCLK 8 and 011B fCLK 2 and the value of the TA0 register is 0000H which is only oriented immediately after the start of counting DMA and EVENTC generate 1 request signal However TAO and TAIO perform alternating outputs In event counter mode regardless of the value of the TCK2 TCK0 bit if ...

Page 238: ...xternal input TAIO in pulse period measurement mode TSTOP The count of timer A forces the stop note 1 If you write 1 to this bit you force the count to stop The read value is 0 TCSTF The count status flag for timer A is noted 2 0 Stop count 1 Counting condition for 0 When writing 0 to the TSTART bit which becomes 0 synchronously with the count source When writing 1 to the TSTOP bit condition for 1...

Page 239: ...he specified polarity of the timer output signal Other than the above Prohibit settings TIPF1 TIPF0 Selection of TAIO input filters 0 0 There is no filter 0 1 There is a filter that samples via the fCLK 1 0 There is a filter that samples via fCLK 8 1 1 There is a filter that samples via fCLK 32 These bits specify the sampling frequency of the TAIO input filter The input to the TAIO pin is sampled ...

Page 240: ...er pattern 0 Count on the rising edge 1 Count on the falling edge Pulse width measurement mode 0 Measure the L level width 1 Measure the H level width Pulse period measurement mode 0 Measure between the rising edge of the measurement pulse and the next rising edge 1 Measure between the falling edge of the measurement pulse and the next falling edge Table 7 5 Polarity switching of TAO output Operat...

Page 241: ... 1 If you select the event counter mode the external input TAIO is selected as the counting source regardless of the setting of TCK0 TCK2 bits 2 You cannot switch the counting source during the counting process If you want to switch the count source you must have 0 in both the TSTART bit and the TSTF bit in the TACR0 register Stop Counting when toggling 3 The operating mode can only be changed whe...

Page 242: ...al the value of the TAISR0 register changes to 00H Figure 7 8 Timer A event pin selects the format of register 0 TAISR0 Address 40042After 243H reset 00HR W Symbol 76543210 TAISR0 RCCPSEL2 Note Timing output signal and selection of INTP4 polarity 0 Events are counted during the L level 1 Events are counted during the H level RCCPSEL1 Note RCCPSEL0 Note Selection of timer output signals 0 0 TMIOD1 ...

Page 243: ...on of port register 0 at 0 To use the multiplexing port P01 TAIO etc of the timer input pin as the input to the timer the position of the port mode register PMxx corresponding to each port must be 1 At this point the bit of the port register Pxx can be 0 or 1 Example The case where P01 is used as a timer input TAIO will place the PM01 position 1 of port mode register 0 Place the P01 position of po...

Page 244: ...ters are reloaded synchronously with the count source the counter is written synchronously with the next count source The rewrite timing diagram determined by the value of the TSTART bit is shown in Figure 7 9 Figure 7 9 Rewritten timing diagram determined by the value of the TSTART bit Counter of TIMER A reload register load signal of counter load clock of counter load clock of reload register lo...

Page 245: ...count source is entered and if the count value becomes 0000H and the next count source is entered an underflow occurs and an interrupt request is generated An example of the timer mode is shown in Figure 7 10 Figure 7 10 An example of a timer mode INTTMA interrupt flag bit TUNDF bit of TACR0 register Counter of TIMER A counting source reload register reload counter underflow occurs accept interrup...

Page 246: ... the TAIOC0 register In addition the output level can be selected by the TEDGSEL bit of the TAIOC0 register An example of the pulse output mode is shown in Figure 7 1 Fig 7 11 Example of operation of pulse output mode TSTART bit of TACR0 register TA0 register Counter of TIMER A TEDGSEL bit of TAIOC0 register corresponding bit of port mode register PMxx used for TAIO functional multiplexing TUNDF b...

Page 247: ...ounter mode refer to the Setup Steps for 7 5 5 TAO Pins and TAIO Pins Example 1 of the operation of the event counter pattern is shown in Figure 7 12 Figure 7 12 Example of running the event counter pattern 1 TAIO pin event input Counter of TIMER A INTTMA interrupt flag bit TUNDF bit of TACR0 register TMOD2 TMOD0 bit of TAMR0 register TSTART bit of TACR0 register control bit of TAIOC0 register acc...

Page 248: ...one towards internal circuit and start counting after operational configuration In order to invalid the change of 2 countin g source clock after counting starts TSTOP bit of TACR0 register shall be set to 1 3 To timer output singal selected by RCCPSEL1 and RCCPSEL0 bit of TAISR0 register the pins which are allocated to the timer output pin can not be used as other multiplex function output INTP4 o...

Page 249: ...TUNDF bit of the TACR0 register becomes 1 underflow occurs and an interrupt request is generated An example of the pulse width measurement mode in operation is shown in Figure 7 14 To access the TEDGF bits and TUNDF bits of the TARCR0 register refer to the 7 5 2 Flag Access TEDGF of the TACR0 register bits and TUNDF bits Fig 7 14 Example of operation of pulse measurement mode measure pulse TAIO pi...

Page 250: ...ource period If the input pulse period and width do not meet these conditions the input pulse may be overlooked Fig 7 15 An example of the operation of the pulse period measurement mode TUNDF bit of TACR0 register TEDGF bit of TACR0 register INTTMA interrupt flag bit TSTART bit of TACR0 register Counter of TIMER A This is the scenario done while TA0 register initial value as 0300H and TEDGSEL bit ...

Page 251: ...ing of the event occurrence source 2 Stop the count of timer A 3 Set the EVENTC s Event Output Destination Selection Register ELSELRn to 0 7 4 8 Output settings for each mode The status of the TAO pins and TAIO pins in each mode is shown in Table 7 6 and Table 7 7 Table 7 6 TAO pin settings Operating mode TAIOC0 register The output of the TAO pin TOENA bit TEDGSEL bit All mode 1 1 Inverting output...

Page 252: ...stop count With the exception of the TCSTF bit the associated register note for timer A cannot be accessed before the TCSTF bit becomes 1 counting If you write 0 stop counting to the TSTART bit during the counting process the TCSTF bit is 1 for 2 CPU clock cycles Stop counting when the TCSTF bit changes to 0 With the exception of the TCSTF bit the associated register note for timer A cannot be acc...

Page 253: ...if the stop count both the TSTART bit and the TSTF bit of the TACR0 register are 0 stop count TAMR0 TAISR0 cannot be changed during the counting process When changing the operating mode correlation registers of timer A the values of the TEDGF and TUNDF bits are indefinite The count must begin after writing 0 to the TEDGF bit no valid edge and 0 to the TUNDF bit no underflow occurred ...

Page 254: ...onding to the TAIO pin to input mode input starting from the TAIO pin 4 Start counting TSTART 1 for TAMR0 registers 5 Wait until the TCSTF bit of the TACR0 register becomes 1 counting Event counter mode only 6 Input external events from the TAIO pin 7 Invalid treatment of the measured value must be performed at the end of the first measurement the second and subsequent measurements are valid Pulse...

Page 255: ... The following SFR cannot be taken in memory after 1 count cycle of the counter s count after the TSTOP bit of the TSTOP bit of the TAC0 register is forced to be stopped TA0 registers TACR0 registers and TAMR0 registers 7 5 11 Digital filters When using a digital filter the timer operation cannot be started within 5 digital filter clock cycles after the TIPF1 bit and the TIPP0 bit of the TAIOC reg...

Page 256: ...ollowing 3 modes Timer Mode The input capturing function counts on the bilateral edges of the rising falling or rising falling edges Output comparison function L level output H level output or alternating output PWM mode PWM output with arbitrary duty cycle Phase count mode Automatically measures the count value of a 2 phase encoder ...

Page 257: ...t comparator fCLK fCLK 2 fCLK 4 fCLK 8 fCLK 32 Data bus Table 8 1 Timer B Pin Structure Pin name The port name of the multiplex Input Output function TBCLK0 P00 input Phase count mode A phase input Input of external clock 0 in non phase counting mode TBCLK1 P01 input Phase count mode B phase input Input of external clock 1 in non phase counting mode TBIO0 P50 Input Output Timer mode output compari...

Page 258: ...l enable register 1 PER1 Timer B mode register TBMR Timer B counts control registers TBCNTC Timer B controls the register TBCR Timer B interrupt enables registers TBIER Timer B status register TBSR Timer BI O control registers TBIOR Timer B counter TB Timer B universal register A TBGRA Timer B universal register B TBGRB Timer B universal register C TBGRC Timer B universal register D TBGRD Port reg...

Page 259: ...er changes to 00H Figure 8 2 format of Peripheral enable register 1 PER1 Address 0x4002081A after reset 00H R W symbol PER1 TMBEN Provides control of the input clock of timer B 0 Stop providing the input clock Cannot write SFR for timer B Timer B is in reset state 1 An input clock is provided SFR can be read and written to timer B Note To set timer B you must first place the TMBEN position 1 When ...

Page 260: ...function When the digital filter function is available up to 5 sampling clock cycles of the digital filter are required for edge detection TBDFA TBIO0 pin digital filter function selection 0 There is no digital filter function 1 There is a digital filter function When the digital filter function is available up to 5 sampling clock cycles of the digital filter are required for edge detection TBMDF ...

Page 261: ...e of the TBCLK0 input CNTEN5 Enable for the count 5 0 void 1 Increment the count When the TBCLK0 input is at the H level and the falling edge of the TBCLK1 input CNTEN4 Enable for the count 4 0 void 1 Increment the count When the TBCLK1 input is the L level and the falling edge of the TBCLK0 input CNTEN3 Enable for the count 3 0 void 1 Decrement the count When the TBCLK1 input is at the H level an...

Page 262: ...atch Other than the above Prohibit settings TBCKEG1 TBCKEG0 Select for the valid edges of the external clock notes 1 and 2 0 0 Count on the rising edge 0 1 Count on the falling edge 1 0 Count on the bilateral edges of the rising falling edges Other than the above Prohibit settings TBTCK2 TBTCK1 TBTCK0 Select for the count source Note 1 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 3...

Page 263: ...VF bits are prohibited 1 Interrupts due to TBOVF bits are valid TBUDIE Underflow interrupts are Enable 0 Interrupts due to TBUDF bits are prohibited 1 Interrupts due to TBUDF bits are valid TBIMIEB Input capture compare matching interrupts allow B 0 Interrupts due to TBIMFB bits are prohibited 1 Interrupts due to TBIMFB bits are valid TBIMIEA Input capture compare matching interrupts enable A 0 In...

Page 264: ...ondition for 0 After reading write 0 Notes 2 and 3 condition for 1 Refer to Conditions for each flag of Table 8 3 as 1 Note 1 When the count value of timer B changes from FFFFH to 0000H the TBOVF bit changes to 1 In addition according to the setting of the TBCCLR bits of the TBCR register and the TBCCLR 1 bits if the count value of timer B is changed from FFFFH becomes 0000H and the TBOVF bit beco...

Page 265: ...pt enables a bit in the interrupt enable register TBIER that is set 1 Enable and the interrupt source status flag for that bit is marked as 1 you must write 0 to both this status flag and the object status flag e g when TBIMIEA clears TBIMFB in a state where interrupts are Enable and TBIMIEB is prohibited Timer B interrupt enables the state of the register TBIER TBIER The status of the timer B sta...

Page 266: ...nderflow occurs limited to phase count mode only TBIMFB Note 2 to the input edge of the TBIO1 pin When the values of TB and TBGRB are the same TBIMFA The input edge of the TBIO0 pin is note 2 When the values of TB and TBGRA are the same Note 1 Phase count mode is a counting method of the timer B count register which can be set to use the above timer mode and PWM mode 2 This is the edge selected by...

Page 267: ...apture function TBIOB1 TBIOB0 TBGRB control 0 0 Disables comparison of matching pin outputs 0 1 Output L level 1 0 Outputs the H level 1 1 Alternate outputs The output of the TB register and tbGRB registers is compared and matched by the output comparison function TBIOB1 TBIOB0 TBGRB control 0 0 Rising edge of TBIO1 0 1 The descending edge of TBIO1 1 0 Bilateral edge of TBIO1 Other than the above ...

Page 268: ...ister to TBGRA via the input capture function Note 1 When TBIOj2 bits j A B are 1 input capture function the TBGRj register is used as the input capture register 2 When the TBIOj2 bit j A B is 0 output comparison function the TBGRj register is used as a comparison match register Set the TBIOj0 bits and TBIOj1 bits after reset and output the following levels from the TBIOj pin before the first comp...

Page 269: ...egisters TBGRB registers or inputs to TBGRA registers and TBGRB registers Register clear 0000H counter clear function When the TB register overflows FFFFH 0000H the TBOVF bit of the TBSR register becomes 1 When the TB register underflows 0000H FFFFH the TBUDF bit of the TBSR register becomes 1 Figure 8 9 Format of the timer B counter TB Address 40042656H After reset 0000H R W Symbol 15 14 13 12 11...

Page 270: ...n also be used as buffer registers for TBGRA registers and TBGRB registers respectively and can pass through the TBBUFA bit sum of the TBIBOR registers The TBBUFB bit selects this feature For example if you set the TBGRA register as the output comparison register and the TBGRC register as the buffer register of the TBGRA register the value of the TBGRC register is passed to each time the compariso...

Page 271: ...omparison register TBIO0 output L level when comparing matches common TBGRC TBIOR TBBUFA 0 Not used TBGRD TBIOR TBBUFB 0 Not used TBGRC TBIOR TBBUFA 1 TBGRA s buffer registers and TBGRA are transmitted When TBIOA2 1 By entering the capture signal the previous input capture value is taken from TBGRA When TBIOA2 0 Through the comparison matching of TB and TBGRA the next comparison expectation is tra...

Page 272: ...When using the multiplex port of the timer input pin as the input to the timer the position of the port mode register PMxx corresponding to each port must be 1 At this point the bit of the port register Pxx can be 0 or 1 Example P50 TBIO0 as a timer input Place the PORT mode register 5 at PM50 position 1 Place the P50 position of port register 5 0 or 1 For details please refer to 2 3 1 Port Mode R...

Page 273: ...K 8 fCLK 32 Select the counting source by the TBTCK0 TBTCK2 bit of the TBCR register TBCLK0 pin and TBCLK1 External input signal for pins The TBCR register has bits 101B TBCLK0 input or 111B in the TBCR register TBCLK1 input Valid edges are selected by the TBCKEG0 bits and TBCKEG1 bits of the TBBCR registers The corresponding bit of the port mode register is 1 input mode Figure 8 12 Block diagram ...

Page 274: ...14 respectively Table 8 6 Buffer operation for each mode Features and modes Transmission timing Registers for transfer Enter the capture function Enter the input of the capture signal Transfers the contents of the TBGRA TBGRB register to the buffer register Output comparison function TB registers and TBGRA TBGRB Comparison matching of registers Transmits the contents of the buffer register to TBGR...

Page 275: ...ister TBGRA register TBGRC register TBIO0 output TB register TBGRA register TBGRC register buffer above diagram condition as following TBBUFA bit of TBIOR register is 1 TBGRC register is the buffer register of TBGRA TBIOA2 TBIOA0 bit of TBIOR register as 001B while compare matching output L voltage level comparator compare matching signal transmit ...

Page 276: ... TBIOj input signal Operational clock of TIMER B perform synchronization through 2 stages trigger sample clock Latches Latches Latches Latches identical signal detection circuit trigger output edge detection circuit TBIOA0 TBIOA2 TBIOB0 TBIOB2 edge detection circuit DFj TBTCK2 TBTCK0 clock period selected via TBDFCLK0 and TBDFCLK1 TBIOj input signal Note j 0 1 TBTCK2 TBTCK0 bits of TBCR register T...

Page 277: ... Table 8 8 respectively Tables 8 7 Events output through TBIMFA bits to EVENTC Features and modes EVENTC source Enter the capture function TBPWM 0 TBIO02 1 TBIO0 edge detection through TBIOA0 bit and TBIOA1 bit settings Output comparison function TBPWM 0 TBIO02 0 Comparison matching of TB registers and TBGRA registers PWM mode TBPWM 1 Comparison matching of TB registers and TBGRA registers Note TB...

Page 278: ... free running 1 fk 65536fk The frequency of the count source Count start criteria Write 1 start counting to the TBSTART bit of the TBBR register Count stop conditions Write 0 stop count to the TBSTART bit of the TBMR register Timing of the generation of interrupt requests Input capture effective edges of TBIO0 pin and TBIO1 pin inputs Overflow of TB registers TBIO0 pin and TBIO1 The function of th...

Page 279: ...rising falling and double edge 2 must set TBSTART bit of TBMR register to 1 and start counting of TB register 2 Enter the timing of the capture signal Input capture inputs can be selected by setting the TBIOR registers on the rising falling or bilateral edges The input signal timing of the input capture is shown in Figure 8 17 In the case of one sided edges the input signal pulse width captured by...

Page 280: ...lected from the rising falling and bilateral edges b The TBSTART position of the TBBMR register must be placed 1 to start counting the TB registers Figure 8 18 an example of an input capture TBGRA register TBGRB register TBIO1 input TBIO0 input Value of TB register TBIO1 0000H 0005H 0160H 0180H Time By setting the TBCLR bits 0 and TBCCLR 1 bits of the TBBCR registers the count can be cleared when ...

Page 281: ...et to 0000H when the TB is set to 0000H when the match is set to 1 fk n 1 n TBGRj register Waveform output timing Comparison matching the contents of the TB register and the TBGRj register are the same Count start criteria Write 1 start counting to the TBSTART bit of the TBBR register Count stop conditions Write 0 stop count to the TBSTART bit of the TBMR register Timing of the generation of inter...

Page 282: ...gister to 1 and start counting of TB register output selection select waveform output mode configure output timing sequence start counting waveform output 1 2 3 2 Output timing for output comparison A comparison match signal is generated when the contents of the TB registers are the same as the contents of the TBGRA registers or the TBGRB registers when the count value after the same TB registers ...

Page 283: ...nd outputs the L level when comparing match A and the H level when comparing match B If the set level is the same as the level of the pin the level of the pin is unchanged Figure 8 21 L level output and H level output operation example TBIO1 output TBIO0 output TBGRA register TBGRB register Value of TB register FFFFH 0000H remain unchanged remain unchanged remain unchanged Time H voltage level out...

Page 284: ...ut pins that match the comparison TBIO0 TBIO1 are not initialized To return to the initial value the output is initialized by writing the TBIOR register however only the TBIO00 bits TBIO01 bits TBIO10 through the TBIOR registers Bits and TBIO11 bits are initialized when they are set to the L level output or the H level output By setting the TBCCLR registers at TBCCLR bits 0 and TBCCLR 1 bits the i...

Page 285: ...ion Count the sources fCLK fCLK 2 fCLK 4 fCLK 8 fCLK 32 TBCLK0 an external input signal from the TBCLK1 pin valid edges are selected programmatically count Increment the count PWM waveform Set the H level output timing of the PWM waveform to the TBGRA registers Set the L level output timing of the PWM waveform to the TBGRB registers Count start criteria Write 1 start counting to the TBSTART bit of...

Page 286: ...must set TBSTART bit of TBMR register to 1 and start counting of TB register PWM mode select clock of the counter select clear source of the counter configure TBGRA configure TBGRB configure PWM mode start counting PWM mode 1 2 3 4 5 6 2 Run the example An example of operation in PWM mode 1 is shown in Figure 8 24 When the PM xx bit of the PM register is 0 and the Pxx bit of the PL register is 0 I...

Page 287: ...duty cycle in PWM mode is shown in Figure 8 25 When the comparison match of the TBGRB register is set to the clear source of the counter and the following conditions are met the duty cycle of the PWM waveform is 0 The setting value of the TBGRA register the setting value of the TBGRB register When the comparison match of tbGRA registers is set to the clear source of the counter and the following c...

Page 288: ...RB register TBIO0 output Value of TB register write configuration value into TBGRA register write configuration value into TBGRA register write configuration value into TBGRB register write configuration value into TBGRB register 0000H clear counter while compare matching B Time a Duty cycle 0 b Duty cycle100 0000H clear counter while compare matching A Time Value of TRG register ...

Page 289: ... Count Mode Item specification Count the sources External input signal from the TBCLK0 TBCLK1 pins count Increment decrement count Count start criteria Write 1 start counting to the TBSTART bit of the TBBR register Count stop conditions Write 0 stop count to the TBSTART bit of the TBMR register Timing of the generation of interrupt requests Input capture effective edges of TBIO0 TBIO1 input Compar...

Page 290: ... register to 1 and start counting of TB register phase counting mode select phase counting mode start counting phase counting mode 1 2 2 Run the example An example of the phase count mode is shown in Figures 8 27 to 8 30 In phase count mode the TBBCLK0 pin is summed up according to the setting of the CNTEN0 CNTEN7 bits of the TBCNTC register The TBCLK1 pin is counted on the double side of the risi...

Page 291: ...t TBCLK0 input Value of TB register Time increment decrement Figure 8 29 Example of the phase count mode 3 while TBCNTC register value as 28H TBCLK1 input TBCLK0 input Value of TB register Time increment decrement Figure 8 30 Example of the phase count mode 4 whlie TBCNTC register value as 5AH TBCLK1 input TBCLK0 input Value of TB register Time increment decrement ...

Page 292: ...Bit0 of the IF1D register when the bit of the TBSR register is 1 and the bit of the corresponding TBIER register is 1 interrupt Enable The bit becomes 1 with interrupt request When multiple bits of the TBIER register are 1 the TBSR register must be used to determine which request source generated the interrupt Because each of the TBSR registers does not automatically change to 0 even if an interru...

Page 293: ...ject status flag e g when TBIMIEA clears TBIMFB in a state where interrupts are Enable and TBIMIEB is prohibited Timer B interrupt enables the state of the register TBIER TBIER The status of the timer B status register TBSR TBSR Because the bit that enables interrupts corresponds to the status flag TBIMFA is 1 so you must write 0 to both TBIMFA and TBIMFB Ban Suspend The bits to clear the request ...

Page 294: ...lse width pulse width phase difference phase difference overlap overlap 8 6 2 Switching modes To switch modes during operation it must be done after the TBSTART position of the TBMR register is 0 stop counting The bit0 of the IF1D register must be set to 0 after switching modes and before starting running For details please refer to Chapter 25 Interrupt Functions 8 6 3 Count the switching of the s...

Page 295: ...of digital filters are required for edge detection 8 6 5 External clocks TBBCLK0 and TBBCLK1 The pulse width of the external clock input to the TBCLKj pin j 0 1 must be at least 3 timer B operating clock fCLK cycles 8 6 6 Read and write access to SFR To set timer B you must first place the TMBEN position of the PER1 register 1 When the TMBEN bit is 0 the write operation of the control register of ...

Page 296: ... snap runs In input capture mode input is given to the TBIO0 TBIO1 pin if the TBSTART bit of the TBBR register is 0 stop count The TBIOj0 bit and TBIOj1 bits of the TBIOR registers are selected at the edges that generate an input capture interrupt request at the effective edge of the TBIO0 TBIO1 input j A B ...

Page 297: ...tor 1 and timer M The actions are as follows Count Start The count action is triggered by software or timer M Count Stop The count stop is triggered by the software or the output of Comparator 1 Input capture When an interrupt from comparator 1 occurs the count value is transferred to the buffer Count Reset The count reset is triggered by timer M or comparator 1 The action clock of Timer C is fCLK...

Page 298: ...om cn 298 1149 Rev 1 02 9 2 Structure of timer C The block diagram of timer C is shown in Figure 9 1 Figure 9 1 Block diagram of timer C Data bus Trigger event from Timer M Trigger event from Comparator 1 Timer C counter source selection Timer control ...

Page 299: ...g clocking hardware that is not in use To use timer C bit1 TMCEN must be set to 1 The PER1 register is set via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 00H Figure 9 2 format of Peripheral enable register 1 PER1 Address 0x4002081A after reset 00H R W symbol PER1 TMCEN Provides control of the input clock of timer C 0 Stop providing ...

Page 300: ...set 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC function Set the scope bit15 0 Increment the count and the TCOVF bit of the TCSR is set to 1 when the overflow occurs 0000H FFFFH 9 3 3 Timer C count buffer register TCBUF Figure 9 4 Format of timer C count buffer register TCBUF Address 0x40042C52 After reset 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCBUF function Set the sc...

Page 301: ...ftware resetting the count counter of Timer C 1 Enables the software to reset the count counter of Timer C Invalid when START_MD 1 TRIG_MD_H W Action selection when Timer C is triggered via the output of Timer M 0 Start counting after resetting Timer C 1 Timer C starts counting Invalid when START_MD 0 TM_TRIG Hardware triggered selection from Timer M 0 The count start action of TM0 T START0 is set...

Page 302: ...e Timer C count stops 0 1 The Timer C count value is passed to the buffer register and the count continues 1 0 The Timer C count value becomes 0000H and the count continues 1 1 The Timer C count is passed to the buffer register the Timer C count value becomes 0000H and the count continues TSTART The Timer C action begins to control the note 0 TheT C count stops 1 TC count starts Note If the stop s...

Page 303: ...1 0 TCSR TCSB Timer C counter status flag bit Note 1 0 Count stops 1 Count TCOVF The Overflow Status Flag bit of the Timer C counter is noted in Note 2 Note 3 0 No overflow occurred 1 An overflow occurred Note 1 Read only not writable Note 2 Only 0 can be written and 1 is invalid Note 3 When the Timer C counter overflow and TCOVF write 0 occur at the same time the overflow has a higher priority 0 ...

Page 304: ...ned by the dividing setting of timer C 1 Clock source for timer C The clock source of timer C is the CPU action clock fclk 2 Timer C counts the clock source Use TCCR1 to set the counting frequency If you use a signal from Timer M to trigger the start of the Timer C count you must set the action clock of Timer C to match the action clock frequency of Timer M 9 4 2 Timer C starts counting the action...

Page 305: ...g 9 8 Example of Timer C count reset and start TRIG_MD_HW 0 TC counter source TCCR1 START_MD TCCR1 TM_TRIG TCCR1 TRIG_MD_HW start signal from TM0 TCCR2 TSTART TC counting TM counting 2 When TRIG_MD_HW 1 the start setup step for the Timer C count a Select the Timer M output signal as the trigger source for counting start TCCR1 START_MD 1 1 2 Select the trigger function of Timer C TCCR1 TRIG_MD_HW 1...

Page 306: ...ct the settings and actions when the software triggers 1 Count Start Source Selection Software Trigger TCCR1 START_MD 0 2 Timer C count start TCCR2 TSTART 1 Fig 9 10 Example of software triggering the start of the Timer C count TC counting source TCCR1 START_MD TCCR2 TSTART TC counting ...

Page 307: ...ng and action when triggered 1 Select Comparator 1 as the trigger TCCR2 CMP1_TCR 00 2 Timer C count starts TCCR2 TSTART 1 Fig 9 11 Example of selecting comparator 1 triggering a stop in Timer C TC counter source TCCR2 CMP1_TCR Interrupt signal of Comparator 1 TCCR2 TSTART TC counting 9 4 3 2 Settings and actions when the software is triggered 1 Timer C count starts TCCR2 TSTART 0 2 Software Settin...

Page 308: ...count starts Fig 9 12 An example of an input captured motion TC counting source TCCR2 CMP1_TC R Interrupt signal of Comparator 1 TCCR2 TSTART TC counting TCBUF 2 Case 2 TCCR2 CMP1_TCR 11 the count value of Timer C is transmitted to the count buffer and the count value of Timer C is reset TCCR2 CMP1_TCR 11 select Input Capture and Reset Function TCCR2 TSTART 1 Timer C count starts Fig 9 13 Example ...

Page 309: ...et counter TCCR1 TRIG_MD_SW 0 3 Timer C count starts TCCR2 TSTART 1 Fig 9 14 Exampleof T imer M triggering a reset of the Timer C count TC counting source TCCR1 START_MD TCCR1 TRIG_MD_SW Start Signal from Timer M TCCR2 TSTART TC counting 2 TRIG_MD_SW 1 the output signal of Timer M resets the count value when the software triggers the count starts 1 Software Trigger Counting Begins TCCR1 START_MD 0...

Page 310: ...resets the count value 1 The count value is reset and the count action continues TCCR2 CMP1_TCR 10 input capture function cannot be used 2 Timer C count starts TCCR2 TSTART 1 Fig 9 16 Example of CMP1 triggering a Timer C count reset TC counting source TCCR2 CMP1_TCR Interrupt signal of CMP1 TCCR2 TSTART TC counting TC buffer ...

Page 311: ... Timer C counter overflows if TCCR1 is set OVIE 1 which produces an overflow interrupt signal Fig 9 17 Example of interrupt generation when the Timer C overflows TC counting source Timer M or software trigger start Timer C frequency divided signal TCCR1 OVIE TC counting TCSR TCOVF TC overflow signal ...

Page 312: ... 000H resets the counter 9 5 3 Input capture and timer C count reset action Even if you set up TCSR TCSB 0 count stop timer M and CMP1 input signals can still trigger Timer C input capture motion and count reset action 9 5 4 Timer C and Timer M comparator 1 are linked When timer C and timer M comparator 1 are linked the setup steps are as follows 1 Provides a clock input for comparator 1 PGACMPEN ...

Page 313: ...a mode that outputs sawtooth wave modulation with no dead time three phase waveforms 6 Complementary PWM mode This is a mode of output triangular wave modulation with dead time three phase waveforms 6 PWM3 mode This is the mode of outputing the same period PWM waveform 2 In timer mode timer M0 and timer M1 have equal input capture functions output comparison functions and PWM functions which can b...

Page 314: ...0 P16 Input Output TMIOD0 P15 Input Output TMIOA1 P12 Input Output TMIOB1 P10 Input Output TMIOC1 P13 Input Output TMIOD1 P11 Input Output TMi registers Timer Mi Count the sources Select the circuit TMGRAi registers TMGRBi register TMGRCi registers TMGRDi registers TMDFi registers TMCRi registers TMIORAi register TMIORCi registers TMSRi registers TMIERi registers TMPOCRi registers TMELC registers ...

Page 315: ...r M control register 0 TMCR0 Timer M I O control register A0 TMIORA0 Timer M I O control register C0 TMIORC0 Timer M state register 0 TMSR0 Timer M interrupt enable register 0 TMIER0 The timer M PWM function outputs level control register 0 TMPOCR0 Timer M meter 0 TM0 Timer M uses register A0 TMGRA0 Timer M uses register B0 TMGRB0 Timer M general purpose register C0 TMGRC0 Timer M general purpose ...

Page 316: ...e input clock 0 Stop providing the input clock Do not write the SFR used in the PWM cut off circuit The PWM cut off circuit is reset 1 An input clock is provided Can read and write SFR used in PWM cut off circuits Note 1 To set the timer M you must first place the TMMEN position 1 When the TMMEN bit is 0 the write operation of the control register of timer M is ignored and the read values are both...

Page 317: ...offs are allowed ELCICE1 Selection of EVENTC event input 1 input capture D1 for timer M 0 Select Input Capture TMIOD1 1 Select Event Input 1 from the Event Linkage Controller EVENTC ELCOBE0 Permissibility of EVENTC event input 0 pulse output for forced cut off timer M 0 Mandatory cut off is prohibited 1 Forced cutoffs are allowed ELCICE0 Selection of EVENTC event input 0 input capture D0 for timer...

Page 318: ...election 0 Stops counting when matching TMGRA0 register comparison 1 Continue counting note 2 after matching with the TMGRA0 register comparison TSTART1 The start flags for the TM1 count note 3 4 0 Stop count 1 Start counting TSTART0 The start flags of the TM0 count note 5 6 0 Stop count 1 Start counting Note 1 PWM3 mode cannot be used 2 When using the input capture feature this position must be 1...

Page 319: ...ter for the TMGRB0 register TMBFC0 TMGRC0 register function selection notes 1 2 0 General Purpose registers 1 Buffer register for TMGRA0 registers TMSYNC Synchronized note 3 for timer M 0 TM0 and TM1 operate independently 1 TM0 and TM1 run synchronously Note 1 When using the output comparison function if you pass the TMIORCi register i 0 1 IOj3 j C or D bit to select 0 change the output pin of the...

Page 320: ...ature selection 0 Input capture function or output comparison function 1 PWM function TMPWMB1 TMIOB1 s PWM feature selection 0 Input capture function or output comparison function 1 PWM function TMPWMD0 TMIOD0 s PWM feature selection 0 Input capture function or output comparison function 1 PWM function TMPWMC0 TMIOC0 s PWM feature selection 0 Input capture function or output comparison function 1 ...

Page 321: ...mentary PWM mode Reset synchronous PWM mode complementary PWM mode 0 Initial output H level L level is valid 1 Initial output L level H level is active Not valid in timer mode and PWM3 mode CMD1 CMD0 Select Notes 2 and 3 for the combination mode In timer mode and PWM3 mode 00B timer mode or PWM3 mode must be set In reset synchronous PWM mode 01B Reset synchronous PWM mode must be set Complementary...

Page 322: ...tput is allowed 1 Disable output TMIOB1 pin is an I O port EA1 Disable note1 and 2 for TMIOA1 output 0 Output is allowed 1 Disable output TMIOA1 pin is an I O port ED0 Disable note 1 for TMIOD0 output 0 Output is allowed 1 Disable output TMIOD0 pin is an I O port EC0 Disable note 1 for TMIOC0 output 0 Output is allowed 1 Disable output TMIOC0 pin is an I O port EB0 TMIOB0 output is prohibited 0 Ou...

Page 323: ... output force cutoff input is invalid 1 The pulse output force cutoff input is valid if the L level is input to the INTP0 pin the TMSHUTS bit is 1 TMSHUTS Force cutoff flags 0 No cutoff is enforced 1 Is in a forced cutoff When the cutoff pulse is forced by the INTP0 pin or an ELC input event this bit becomes 1 and is not automatically cleared Therefore to stop the forced cutoff pulse you must writ...

Page 324: ... Initial Output Level Selection Note 1 0 Initial output L level 1 Initial output H level TOA1 Selection of the initial output level of TMIOA1 0 Initial output L level 1 Initial output H level TOD0 Select Note 1 for the initial output level of TMIOD0 0 Initial output L level 1 Initial output H level TOC0 TMIOC0 Initial Output Level Selection Note 1 0 Initial output L level 1 Initial output H level ...

Page 325: ... level TOA1 Selection of the initial output level of TMIOA1 must set to 0 TOD0 Select Note 1 for the initial output level of TMIOD0 0 The initial output is an invalid level 1 The initial output is the effective level TOC0 TMIOC0 Initial Output Level Selection Note 1 0 The initial output is an invalid level 1 The initial output is the effective level Valid in reset synchronous PWM mode and compleme...

Page 326: ...l Output Level Selection Note 1 0 The initial output L level the H level is valid Outputs the H level when TBGRB1 compares the match and the L level when the TBGRB0 compares the match 1 The initial output H level the L level is valid Outputs the L level when THE TCPRB1 compares the match and the H level when the TBGRB0 compares the match TOA0 Selection of the initial output level of TMIOA0 0 The i...

Page 327: ... 5 sampling clock cycles of the digital filter are required for edge detection DFC TMIOCi pin of digital filter function selection 0 There is no digital filter function 1 There is a digital filter function When the digital filter function is available up to 5 sampling clock cycles of the digital filter are required for edge detection DFB TMIOBi pin digital filter function selection 0 There is no d...

Page 328: ...tput 1 0 L level output 1 1 H level output If the corresponding pin is not used as the output port for timer M in these modes it must be set to 00B forced cutoff is prohibited Also these bits must be set during the stop count process DFD DFC Control of pulse forced cutoff at the TMIOC pin 0 0 Mandatory cut off is prohibited 0 1 High impedance output 1 0 L level output 1 1 H level output If the cor...

Page 329: ...imers Mi Note 1 1 0 1 Clears when input capture compare matches for TMGRCi 1 1 0 Clears when TMGRDi s input capture compare matches Other than the above Prohibit settings CKEG1 CKEG0 Select note 2 for the external clock edge 0 0 Count on the rising edge 0 1 Count on the falling edge 1 0 Count on the bilateral edge Other than the above Prohibit settings TCK2 TCK1 TCK0 Count the selection of sources...

Page 330: ...ternal clock edge 0 0 Count on the rising edge 0 1 Count on the falling edge 1 0 Count on the bilateral edge Other than the above Prohibit settings TCK2 TCK1 TCK0 Count the selection of sources 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 32 1 0 1 Input note 2 for TMCLK Other than the above Prohibit settings Note 1 The TCK2 TCK0 bit is 101B the input to TMCLK and the STCLK bit is 1...

Page 331: ... clock edge 0 0 Count on the rising edge 0 1 Count on the falling edge 1 0 Count on the bilateral edge Other than the above Prohibit settings TCK2 TCK1 TCK0 Count the selection of sources 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 32 1 0 1 Input note 2 for TMCLK Other than the above Prohibit settings Note 1 The TCK2 TCK0 bit is 101B the input to TMCLK and the STCLK bit is 1 Valid...

Page 332: ...ilateral edge Other than the above Prohibit settings TCK2 TCK1 TCK0 Count the selection of sources 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 32 1 0 1 Input note 3 for TMCLK Other than the above Prohibit settings Note 1 The TCK2 TCK0 bit is 101B the input to TMCLK and the STCLK bit is 1 Valid when external clock input valid 2 TCK0 to TCK2 bits CKEG0 bits CKEG0 bits and CKEG1 regi...

Page 333: ...CCLR1 CCLR0 Clear selection for the TM0 counter 001B must be set clear the TM0 register when matching the TMGRA0 register CKEG1 CKEG0 Selection of external clock edges Not valid in PWM3 mode TCK2 TCK1 TCK0 Count the selection of sources 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 32 Other than the above Prohibit settings 7 6 5 4 3 2 1 0 CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0...

Page 334: ...hibit settings IOA2 TMGRA mode selection note 2 When using the input capture function you must set 1 input capture IOA1 IOA0 TMGRA control 0 0 The input is captured to the THEMGRAi on the rising edge 0 1 The input is captured to the THEMGRAi on the falling edge 1 0 The input is captured on both sides to the THEMGRAi Other than the above Prohibit settings Note 1 If you select 1 buffer register of t...

Page 335: ...ode selection note 2 When using the output comparison function you must set 0 output comparison IOA1 IOA0 TMGRA control 0 0 Disables comparison of matching pin outputs TMIOAi pins are I O ports 0 1 Outputs the L level when the TMGRAi comparison matches 1 0 Outputs the H level when the TMGRAi comparison matches 1 1 Alternate outputs are performed when the TMGRAi comparison matches Note 1 If you sel...

Page 336: ...t settings IOC3 Selection of TMGRC register function When using the input capture function a 1 general purpose register or buffer register must be set IOC2 TMGRC mode selection note 2 When using the input capture function you must set 1 input capture IOC1 IOC0 TMGRC control 0 0 The input is captured to the TMGRCi on the rising edge 0 1 The input is captured to the TMGRCi on the falling edge 1 0 Th...

Page 337: ...GRC register function 0 TMIOA output registers Refer to Changes to the Output Pins of the 10 5 2 2 TMGRCi Register and the TMGRDi Register i 0 1 1 General Purpose registers or buffer registers IOC2 TMGRC mode selection note 2 When using the output comparison function you must set 0 output comparison IOC1 IOC0 TMGRC controlled 0 0 Disables comparison of matching pin outputs 0 1 Outputs the L level ...

Page 338: ...After reading write 0 Note 2 condition for 1 The input edge of the TMIOC0 pin is note 3 IMFB Enter the capture compare match flag B Note 5 condition for 0 After reading write 0 Note 2 condition for 1 Note 4 on the input edge of the TMIOB0 pin IMFA Enter the capture compare match flag A note 5 condition for 0 After reading write 0 Note 2 condition for 1 The input edge of the TMIOA0 pin is note 4 No...

Page 339: ...register i TMIERi has a bit placed 1 allowed and the interrupt source status flag allowed by that bit is 0 the object status flag must be written 0 e g in the case where IMIEA and OVIE clear IMFB in a state where interrupts are allowed and IMIEB is prohibited Timer M interrupt enable the state of register i TMIERi 0 0 0 OVIE 1 IMIED 0 IMIEC 0 IMIEB 0 IMIEA 1 interrupt enable interrupt disable TMIE...

Page 340: ...ng status flag OVF IMFA of enabled interrupt are 0 TMSRi 3 This is the edge of the IOk1 bit and IOk0 bit k C or D selected for the TMIORC0 register Includes the case where the TMBFk0 bit of the TMMR register is 1 TMGRk0 is the buffer register 4 This is the edge of the IOj1 bit and IOj0 bit j A or B selected for the TMIORA0 register 5 When using DMA IMFA bits IMFB bits IMFC bits and IMFD bits becom...

Page 341: ...on for 0 Read 0 note 1 condition for 1 Note 3 when the values of TM0 and TMGRD0 are the same IMFC Enter the capture compare match flag C Note 4 condition for 0 Read 0 note 1 condition for 1 Note 3 when the values of TM0 and TMGRC0 are the same IMFB Enter the capture compare match flag B Note 4 condition for 0 Read 0 note 1 condition for 1 When the values of TM0 and TMGRB0 are the same IMFA Enter c...

Page 342: ...register i TMIERi has a bit placed 1 allowed and the interrupt source status flag allowed by that bit is 0 the object status flag must be written 0 e g in the case where IMIEA and OVIE clear IMFB in a state where interrupts are allowed and IMIEB is prohibited Timer M interrupt enable the state of register i TMIERi 0 0 0 OVIE 1 IMIED 0 IMIEC 0 IMIEB 0 IMIEA 1 interrupt enable interrupt disable TMIE...

Page 343: ...f timer M0 changes from FFFFH to 0000H the overflow flag changes to 1 In addition according to the setting of the CCLR0 CCLR2 bit of the TMCR0 register if the input capture or comparison match occurs during operation the count value of timer M0 is changed from FFFFH becomes 0000H and the overflow sign becomes 1 3 This includes cases where the TMBFk0 bit k C or D of the TMMR register is 1 TMGRk0 is...

Page 344: ...ter the capture compare match flag C Note 5 condition for 0 After reading write 0 Note 2 condition for 1 The input edge of the TMIOC1 pin is note 3 IMFB Enter the capture compare match flag B Note 5 condition for 0 After reading write 0 Note 2 condition for 1 The input edge of the TMIOB1 pin is note 4 IMFA Enter the capture compare match flag A note 5 condition for 0 After reading write 0 Note 2 c...

Page 345: ...ble register i TMIERi has a bit placed 1 allowed and the interrupt source status flag allowed by that bit is 0 the object status flag must be written 0 e g in the case where IMIEA and OVIE clear IMFB in a state where interrupts are allowed and IMIEB is prohibited Timer M interrupt enable the state of register i TMIERi 0 0 0 OVIE 1 IMIED 0 IMIEC 0 IMIEB 0 IMIEA 1 interrupt enable interrupt disable ...

Page 346: ...e bit is 1 it is necessary to write 0 to IMFA and IMFB at the same time TMSRi 3 This is the edge of the IOk1 bit and IOk0 bit k C or D selected for the TMIORC1 register This includes cases where the TMBFk1 bit of the TMMR register is 1 TMGRk1 is the buffer register 4 This is the edge of the IOj1 bit and IOj0 bit j A or B selected for the TMIORA1 register 5 When using DMA IMFA bits IMFB bits IMFC b...

Page 347: ...an overflow occurs in TM1 IMFD Enter capture compare match flag D Note 4 condition for 0 Read 0 note 1 condition for 1 Note 3 when the values of TM1 and TMGRD1 are the same IMFC Enter the capture compare match flag C Note 4 condition for 0 Read 0 note 1 condition for 1 Note 3 when the values of TM1 and TMGRC1 are the same IMFB Enter the capture compare match flag B Note 4 condition for 0 Read 0 no...

Page 348: ...ble register i TMIERi has a bit placed 1 allowed and the interrupt source status flag allowed by that bit is 0 the object status flag must be written 0 e g in the case where IMIEA and OVIE clear IMFB in a state where interrupts are allowed and IMIEB is prohibited Timer M interrupt enable the state of register i TMIERi 0 0 0 OVIE 1 IMIED 0 IMIEC 0 IMIEB 0 IMIEA 1 interrupt enable interrupt disable ...

Page 349: ...MFB at the same time TMSRi 2 When the count value of timerM1 changes from FFFFH to 0000H the overflow flag changes to 1 In addition according to the setting of the CCLR0 CCLR2 bit of the TMCR1 register if the count value of timer M1 is changed from FFFFH becomes 0000H and the overflow sign becomes 1 3 This includes cases where the TMBFk1 bit k C or D of the TMMR register is 1 TMGRk1 is the buffer ...

Page 350: ...t capture comparison matching interrupts allow D 0 Interrupts IMID due to IMFD bits are prohibited 1 Interrupts IMIDs due to IMFD bits are allowed IMIEC Input capture compare matching interrupts allow C 0 Interrupts due to IMFC bits IMIC are prohibited 1 Interrupts due to IMFC bits IMCs are allowed IMIEB Input capture compare matching interrupts allow B 0 Interrupts due to IMFB bits IMIB are prohi...

Page 351: ... the timer PWM Function Address 0x40042A75 TMPOCR0 0x40042A85 TMPOCR1 after reset 00H R W symbol TMPOCRi BOLT The output level control of the PWM function D 0 The TMIODi output level is active at the L level 1 The TMIODi output level is active at H level SHELF The output level control of the PWM function C 0 The TMIOCi output level is active at L level 1 The TMIOCi output level is active at H leve...

Page 352: ...its not 8 bits Figure 10 30 Format of timer M counter i TMi i 0 1 timer mode Address 0x40042A76 TM0 0x40042A86 TM1 after reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMi function Configure range bit15 0 Increment the count on the count source If an overflow occurs the OVF bit of the TMSRi register becomes 1 0000H FFFFH Figure 10 31 Format of the timer M counter i TMi i 0 1 Reset Sy...

Page 353: ... must be set Increment or decrement counts on the count source If an overflow occurs the OVF bit of the TMSR0 register becomes 1 0001H FFFFH Figure 10 33 Format of the timer M counter i TMi i 0 1 Complementary PWM Mode TM1 Address 0x40042A76 TM0 0x40042A86 TM1 after reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMi function Configure range bit15 0 Must be set to 0000H Increment or d...

Page 354: ...be accessed in 16 bits not 8 bits In reset synchronous PWM mode the following registers are invalid TMPMR TMOCRnote TMDF0 TMDF1 TMIORA0 TMIORC0 TMPOCR0 TMIORA1 TMIORC1 TMPOCR1 Note As the initial output setting of TMIOC0 in reset synchronous PWM mode and complementary PWM mode only the TOC0 bit of the TMOCR register is valid Complementary PWM mode The TMGRAi TMGRDi registers must be accessed in 16...

Page 355: ... 0x40042A78 TMGRA0 0x40042A7A TMGRB0 After reset FFFFH R W 0x40042B58 TMGRC0 0x40042B5A TMGRD0 0x40042A88 TMGRA1 0x40042A8A TMGRB1 0x40042B5 C TMGRC1 0x40042B5E TMGRD1 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMGRAi TMGRBi TMGRCi TMGRDi function bit15 0 Refer to Table 10 3 TMGRji Register Function When Using the Input Capture Function Table 10 3 Uses the TMGRji register function when using the...

Page 356: ...n TMBFki IOj3 TMGRAi A general purpose register that must write the comparison value TMIOAi TMGRBi TMIOBi TMGRCi 0 1 A general purpose register that must write the comparison value TMIOCi TMGRDi TMIODi TMGRCi 1 1 Buffer registers which must write down the next comparison value See 10 4 2 Buffer Run TMIOAi TMGRDi TMIOBi TMGRCi 0 0 TMIOAi output control Refer to Changes to the Output Pins of the 10 ...

Page 357: ... purpose registers the PWM period must be set TMGRBi A general purpose register where the change point of the PWM output must be set TMIOBi TMGRCi TMBFCi 0 A general purpose register where the change point of the PWM output must be set TMIOCi TMGRDi TMBFDi 0 TMIODi TMGRCi TMBFCi 1 Buffer register the next PWM period must be set refer to 10 4 2 Buffer Run TMGRDi TMBFDi 1 Buffer register the change ...

Page 358: ...ister where the change point of the PWM2 output must be set TMIOA1T MIOC1 TMGRB1 A general purpose register where the change point of the PWM3 output must be set TMIOB1T MIOD1 TMGRC1 TMBFC1 0 Not used in reset synchronous PWM mode TMGRD1 TMBFD1 0 TMGRC0 TMBFC0 1 Buffer register the next PWM period must be set refer to 10 4 2 Buffer Run TMIOC0 is per PWM Period for inverting output TMGRD0 TMBFD0 1 ...

Page 359: ... i 0 1 Complementary PWM mode Address 0x40042A78 TMGRA0 0x40042A7A TMGRB0 After reset FFFFH R W 0x40042B58 TMGRC0 0x40042B5A TMGRD0 0x40042A88 TMGRA1 0x40042A8A TMGRB1 0x40042B5C TMGRC1 0x40042B5E TMGRD1 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMGRAi TMGRBi TMGRCi TMGRDi function bit15 0 Refer to TABLE 10 7 COMPLEMENTARY PWM MODE IN THE TBGRJI REGISTER FUNCTION ...

Page 360: ...ue of the TM0 register When the TSTART0 bit and TSTART1 bit of the TMSTR register are 1 This register cannot be written when Start Count TMIOA1T MIOC1 TMGRB1 A general purpose register where the change point of the PWM3 output must be set at the initial setup Setting range The setting value initial value of the count of the TM0 register The setting value for TMGRB1 Setting value of TMGRA0 The sett...

Page 361: ...value of the TMGRB1 register must be set at the initial setup MIOD1 Note if you put the TCK2 TCK0 position of the TMCRi register 000B fCLK fHOCO And set the comparison value to 0000H to generate a request signal to the DMA and ELC only after starting the count If the comparison value is greater than or equal to 0001H a request signal is generated at each time the comparison matches Remark i 0 1 j ...

Page 362: ...RCi TMGRDi i 0 1 format PWM3 Mode Address 0x40042A78 TMGRA0 0x40042A7A TMGRB0 After reset FFFFH R W 0x40042B58 TMGRC0 0x40042B5A TMGRD0 0x40042A88 TMGRA1 0x40042A8A TMGRB1 0x40042B5C TMGRC1 0x40042B5E TMGRD1 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMGRAi TMGRBi TMGRCi TMGRDi function bit15 0 Refer to TMGRji Register Functions in Table 10 8PWM3 Mode ...

Page 363: ...BFC0 0 Not used in PWM3 mode TMGRC1 TMBFC1 0 TMGRD0 TMBFD0 0 TMGRD1 TMBFD1 0 TMGRC0 TMBFC0 1 Buffer register the next PWM period must be set refer to 10 4 2 Buffer Run Setting range The setting value of the TMGRC1 register the setting value of TMGRC0 TMIOA0 TMGRC1 TMBFC1 1 Buffer register the change point of the next PWM output must be set see 10 4 2 Buffer Run Setting range The setting value of T...

Page 364: ...egister PMCxx is at position 0 At this point the bit of the port register Pxx can be 0 or 1 Example P10 TMIOD1 as a timer input Place the PM10 position of Port Mode Register 1 1 Place the PMC10 position of port mode register 1 0 Place the P10 position of port register 1 at 0 or 1 Set the PM1 and PMC1 registers via the 8 bit memory operation instructions After generating a reset signal the value of...

Page 365: ... register is 1 the external clock input is valid The TCK2 TCK0 bits of the TMCRi register are 101B the counting source is an external clock The effective edge is selected by the CKEG1 to CKEG0 bits of the TMCRi register The bit of the port mode register of the multiplexed I O port of the TMCLK pin is 1 input mode Note i 0 1 Figure 10 41 Block diagram of counting source selection FRQSEL4 0 FRQSEL4 ...

Page 366: ...d TMGRBi registers Transfer the contents of the TMGRDi register buffer register to the TMGRBi register PWM function Comparison matching of TMi registers and TMGRAi registers Transfer the contents of the TMGRCi register buffer register to the TMGRAi register Comparison matching of TMi registers and TMGRBi registers Transfer the contents of the TMGRDi register buffer register to the TMGRBi register ...

Page 367: ...son function Note i 0 1 The conditions in the above figure are as follows The TMBFCi bit of the TMMR register is 1 the TMGRCi register is the buffer register of the TMGRAi register The IOA2 IOA0 bit of the TMIORAi register is 001B when the comparison matches the output L level transmission n TMGRCi registers Buffer TMGRAi register TMi registers TMGRAi registers TMGRCi registers Buffer TMIOAi outpu...

Page 368: ...position of the TMIORCi register must be 1 general purpose register or buffer register The IOD2 bit of the TMIORCi register must be set to the same value as the IOB2 bit of the TMIORAi register When using the input capture function even if the TMGRCi register and the TMGRDi register are used as buffer registers the TMSRi registers are used on the input edge of the TMIOCi pin and the TMIODi pin The...

Page 369: ...CR1 register is 011B simultaneous clear the TM1 register and TM0 registers become 0000H at the same time Figure 10 44 runs synchronously The conditions in the above figure are as follows The TMSYNC bit of the TMMR register is 1 synchronous operation The CCLR2 CCLR0 bit of the TMCR0 register is 001B when entering the capture the TM0 is set to 0000H The CCLR2 CCLR0 bit of the TMCR1 register is 011B ...

Page 370: ...ter is either TMDF1 registers for DFCK1 DFCK0 PENB1 PENB0 DFD the output values of the DFC DFB and DFA bit settings are output from the output pins used as the M output port for the timer When you use this feature you must make the following settings Pin state high impedance L level output or H level output when the pulse output is forced to cut off through the TMDFi registers For pulse forced cut...

Page 371: ...data TIMER M output data multiplex I O port output data HI Z selection signal PMxx input data TMIOA0 PENB1 PENB0 TMIOB0 TIMER M output data multiplex I O port output data HI Z selection signal PMxx input data DFD DFC TMIOC1 TIMER M output data multiplex I O port output data PMxx input data DFB DFA TMIOD1 ELCOBE0 ELCOBE1 TMELC register bits TMPTO TMSHUTS TMOER2 register bits PMXx PM register bits D...

Page 372: ...OBEi bits i 0 1 Set 1 10 4 6 Event output to the Event Linkage Controller EVENTC Data Transfer Controller DMA The mode of timer M and the events output to EVENTC DMA are shown in Table 10 11 Table 10 11 Timer M Modes and Events Output to ELC DMA Usage patterns Output source EVENTC DMA Enter the capture function TMIOA0 edge detection through IOA1 bit and IOA0 bit settings of TMIORA0 registers TMIOB...

Page 373: ...i 0 1 j A B C D will be The contents of the TMi register counter are transferred to the TMGRji register input capture Because the TMIOji pin and the TMGRji register are used in combination they can be pin selected as input capture functions or other modes and functions The block diagram and running example of the input capture function are shown in Figures 10 46 and 10 47 respectively and the spec...

Page 374: ...rol circuit transmit signal TMBFC0 0 TMGRC0 as general register 1 TMGRC0 as buffer register TMGRC0 Timer M general register C0 IMFA0 edge detection digital filter function IOC1 IOC0 00B rising edge 01B falling edge 10B double edge DFC 0 Filter function invalid 1 Filter function valid Pxx TMIOC0 PMxx transmit control circuit edge detection digital filter function IOB1 IOB0 00B rising edge 01B falli...

Page 375: ...B0 TMIOC0 TMIOD0 TMIOA1 TMIOD1 pin function I O ports or inputs captured by pins INTP0 pin function Not used input private port or INTP0 interrupt input Read timer If you read the TMi register you can read the count value Write timer Write the TMi register when the TMSYNC bit of the TMMR register is 0 timer M0 and timer M1 operate independently If you write the TMi register when the TMSYNC bit of ...

Page 376: ... 1 at the same time Figure 10 47 An example of an input capture function TMCLK input counting source TMi register counting value FFFFH 0009H 0006H 0000H time TSTARTi bit of TMSTR register 65536 TMDIOAi input 0006H 0009H TMGRAi register 0006H TMGRCi register IMFA bit of TMSRi register OVF bit of TMSRi register transmit transmit set to 0 via program Note i 0 1 above diagram condition as following CC...

Page 377: ...ection circuit trigger output edge detection circuit DFj 1 IOA2 IOA0 IOB2 IOB0 IOC3 IOC0 IOD3 IOD0 edge detection circuit 0 101B 100B 011B 010B 001B 000B TMCLK fCLK 32 fCLK 8 fCLK 4 fCLK 2 fCLK fHOCO Note 1 fCLK 32 Note 2 fCLK 8 fCLK 00B 01B 10B 11B TCK2 TCK0 DFCK1 DFCK0 sample clock Note 2 Note 2 clock period selected via TCLK2 TCLK0 or DFCLK1 DFCLK0 as long as 1 out of 3 times the signal is not ...

Page 378: ... output any level from the TMIOji pin Because of the TMIOji pin and the TMGRji Registers are used in combination so that pin selection can be made for output comparison functions or other modes and functions The block diagram and operation example of the output comparison function are shown in Figures 10 49 and 10 50 respectively and the specifications of the output comparison function are shown i...

Page 379: ...equests Comparison matching TMi registers and TMGRji registers have the same content Overflow of TMi TMIOA0 pin function I O port output for output comparison or TMCLK external clock input TMIOB0 TMIOC0 TMIOD0 TMIOA1 TMIOD1 pin function I O ports or outputs for output comparison selected by pin INTP0 pin function Not used input private port or INTP0 interrupt input Read timer If you read the TMi r...

Page 380: ...e of the TMGRAi register n The setting value of the TMGRBi register p The setting value of the TMGRCi register The conditions in the above figure are as follows The CSELi bit of the TMSTR register is 1 TMi does not stop when the comparison matches The TMBFCi bits and TMBFDi bits of the TMMR registers are 0 TMGRCi and TMGRDi do not operate as buffers The EAi bits of the TMOER1 register the EBi bits...

Page 381: ...ster TMIOC1 register TM0 TMGRA0 TMGRC0 TMGRB0 TMGRD0 TM1 TMGRA1 TMGRC1 TMGRB1 TMGRD1 compare matching signal compare matching signal compare matching signal compare matching signal compare matching signal compare matching signal compare matching signal compare matching signal Timer RD1 output control output control output control output control output control output control output control output c...

Page 382: ...am set to 0 via program set to 0 via program inverted phase output while compare matching Initial output L voltage level value in Tmi register counting source Time Note i 0 1 m The setting value of the TMGRAi register n The setting value of the TMGRBi register p The setting value of the TMGRCi register q The setting value of the TMGRDi register The conditions in the above figure are as follows The...

Page 383: ... TMIORAi register are 011B TMIOAi inverts the output when the TMGRAi comparison matches The IOB2 IOB0 of the TMIORAi register is 011B TMIOBi inverts the output when the TMGRBi comparison matches The IOC3 IOC0 of the TMIORCi register is 0011B TMIOAi inverts the output when the TMGRCi comparison matches The IOD3 IOD0 of the TMIORDi register is 1000B TMIOBi inverts the output when the T MGRCi compari...

Page 384: ...cut off 1 enable force cut off use to force cut off EVENTC event0 ELCOBE0 0 disable force cut off 1 enable force cut off use to force cut off EVENTC event1 ELCOBE1 0 disable force cut off 1 enable force cut off TMSHUTS 0 force cut off not occurs 1 force cut off occurs Pxx TMIOA0 TMCLK TMCLK PMxx counter clear signal transmit signal TMBFC0 0 TMGRC0 as compare register 1 TMGRC0 as buffer register tr...

Page 385: ...e TMSTR register is 0 and a comparison match of TMGRAi occurs The PWM output pins remain relatively matched after the output changes Timing of the generation of interrupt requests Comparison matching TMi registers and TMGRhi registers have the same content Overflow of TMi TMIOA0 pin function I O port or TMCLK external clock input TMIOA1 pin function I O port TMIOB0 TMIOC0 TMIOD0 TMIOB1 TMIOC1 TMIO...

Page 386: ...alid set to 0 via program set to 0 via program set to 0 via program set to 0 via program Time H voltage valid Note i 0 1 m The setting value of the TMGRAi register n The setting value of the TMGRBi register p The setting value of the TMGRCi register q The setting value of the T MGRDi register The conditions in the above figure are as follows The TMBFCi bits and TMBFDi bits of the TMMR registers ar...

Page 387: ...it of TMSTR register TMIOBi output TMGRBi register IMFA bit of TMSRi register IMFB bit of TMSRi register if both TMGRAi and TMGRBi register compare matching occur at the same time TMGRBi register compare matching takes the priority TMIOBi output L voltage level unchanged TMIOBi will not output L voltage level unchanged when TMGRBi register compare matching occurs modified via program set to 0 via ...

Page 388: ... and 3 inverted phases 6 in total The block diagram and operation example of the reset synchronous PWM mode are shown in Figures 10 56 and 10 57 respectively and the specifications of the reset synchronous PWM mode are shown in Table 10 15 For examples of PWM operations with duty cycles of 0 and 100 please refer to Examples of PWM operations in Figure 10 55 Figure 10 56 Block diagram of reset sync...

Page 389: ...en the CSEL0 bit of the TMSTR register is 0 and a comparison match of TMGRA0 occurs The PWM output pin outputs the initial output level of the OLS0 bit and OLS1 bit selection of the TMFCR register Timing of the generation of interrupt requests Comparison matching TM0 registers have the same content as TMGRj0 TMGRA1 TMGRB1 registers Overflow of TM0 TMIOA0 pin function I O port or TMCLK external clo...

Page 390: ...ogram set to 0 via program set to 0 via program set to 0 via program transmit from buffer register to general register while buffer is in operation transmit from buffer register to general register while buffer is in operation Initial output H voltage level L voltage valid L voltage valid Initial output H voltage level Time Note i 0 1 m The setting value of the TMGRA0 register n The setting value ...

Page 391: ...force cut off 00B remains 10B output L 01B outputHi Z 11B output H TMGRA1 Timer M general register A1 compare comparator circuit output voltage control EA1 0 enable output 1 disable output force cut off control Pxx PMxx compare matching signal inverted phase output signal IMFA1 OLS0 0 Initial output H voltage level valid voltage level is L 1 Initial output L voltage level valid voltage level is H ...

Page 392: ...start counting to the TSTART0 bits and TSTART1 bits of the TMSTR register Count stop conditions When the CSEL0 bit of the TMSTR register is 1 write 0 stop count to the TSTART0 bit and TSTART1 bit The PWM output pin outputs the initial output level of the OLS0 bit and OLS1 bit selection of the TMFCR registers Timing of the generation of interrupt requests Comparison matching TMi registers and TMGRj...

Page 393: ...eration example Fig 10 59 Output model of complementary PWM mode The value of the TMi register TMGRA0The value of the register The value of the TMGRB0 register The value of the TMGRA1 register The value of the TMGRB1 register 0000H time TMIOB0 output TMIOD0 output TMIOA1 output TMIOC1 output TMIOB1 output TMIOD1 output TMIOC0 output Note i 0 1 ...

Page 394: ...am modified via program set to 0 via program L voltage valid Initial output H voltage level Initial output H voltage level positive phase valid voltage width inverted phase valid voltage width change to FFFFH Time transmit CMD1 bit and CMD0 bit as 11B scenario transmit CMD1 bit and CMD0 bit as 10B scenario dead time Note CMD0 CMD1 Bit of the TMFCR register i 0 1 m The setting value of the TMGRA0 r...

Page 395: ...ge level valid voltage level is output H 1 Initial output H voltage level valid voltage level is output L Pxx PMxx TMBFC0 1 TMGRC0 as buffer register TMBFD0 1 TMGRD0 as buffer register compare matching signal output voltage control EA0 0 enable output 1 disable output force cut off control PWMOP DFCK1 DFCK0 pin state during force cut off 00B remains 10B output L 01B output Hi Z 11B output H Genera...

Page 396: ... count to the TSTART0 bit when the CSEL0 bit of the TMSTR register is 1 The PWM output pin holds the output level before stopping the count Stop counting when the CSEL0 bit of the TMSTR register is 0 and a comparison match of TMGRA0 occurs The PWM output pins remain relatively matched after the output changes Timing of the generation of interrupt requests Comparison matching TMi registers and TMGR...

Page 397: ...et to 0 via program set to 0 via program set to 0 via program Initial output L voltage level set to 0 via program Time Stop counting next data transmit transmit perform transmission from buffer register to general register Remark j A B m The setting value of the TMGRA0 register n The setting value of the TMGRA1 register p The setting value of the TMGRB0 register q The setting value of the T MGRB1 ...

Page 398: ...10 63 Table 10 18 Timer M interrupt related registers Status register for timer M Interrupts of timer M enable registers Interrupt request flag Register Interrupt mask flag Register Timer M0 TMSR0 TMIER0 TMIF0 IF2H TMMK0 MK2H Timer M1 TMSR1 TMIER1 TMIF1 IF2H TMMK1 MK2H Figure 10 63 Block diagram of timer M interrupt Timer Mi Timer Mi interrupt request i 0 1 IMFA IMFB IMFC IMFD OVF UDF TMSri regist...

Page 399: ...tatus flag must be written 0 after setting the timer M interrupt enable register i TMIERi to 00H disable all interrupts b When the timer M interrupt enable register i TMIERi has a bit placed 1 allowed and the interrupt source status flag allowed by that bit is 0 the object status flag must be written 0 e g in the case where IMIEA and OVIE clear IMFB in a state where interrupts are allowed and IMIE...

Page 400: ... cn 400 1149 Rev 1 02 The status of the timer M status register i TMSRi 0 0 UDF 0 OVF 0 IMFD 1 IMFC 0 IMFB 1 IMFA 1 must cclear request bit The status flag IMFA corresponding to the interrupt enable bit is 1 so both IMFA and IMFB must be written 0 TMSRi ...

Page 401: ...sition 1 Even if you write 1 and 0 to the CSELi bit and the TSTARTi bit at the same time using 1 instruction the count cannot be stopped The output level during the count stop when the TMIOji pin j A B C D is used for the timer M output as shown in Table 10 19 as shown The output levels of the TMIOji pins j A B C D when Table 10 19 stop counts The method that stops counting Stop counting the outpu...

Page 402: ...or TMIOAi TMIOBi TMIOCi TMIODi pins After reset the multiplexed I O ports of the TMIOAi TMIOBi TMIOCi TMIODi pins are used as input ports To output from the TMIOAi TMIOBi TMIOCi TMIODi pins you must follow the steps below to set them Change Step 2 Set the mode and initial values 3 Place the TMUAi TMIOBi TMIOCi TMIODi pins as allowed outputs TMOER1 registers 4 Place the port registers at 0 correspo...

Page 403: ...complementary PWM mode 4 Reset the other associated registers for timer M Change Step Case of Discontinuation of Complementary PWM Mode 1 Both the TSTART0 bits and the TSTART1 bits of the TMSTR register are set to 0 stop count 2 Place cmD1 bit and CMD0 position 00B timer mode PWM mode and PWM3 mode TMGRA0 TMGRB0 TMGRA1 TMGRB1 registers cannot be written during operation To change the PWM waveform ...

Page 404: ...1 0 FFFFH the UDF bit of the TMSRi register becomes 1 When the CMD1 bit and CMD0 bit of the TMFCR register are 10B complementary PWM mode in TM1 Transmit buffer data when underflow occurs the contents of the buffer registers TMGRD0 TMGRC1 TMGRD1 are transferred to the General Purpose registers TMGRB0 TMGRA1 TMGRB1 When performing an increment count of FFFFH 0 1 the data is not transferred to regis...

Page 405: ...0 66 Example of operation when the value of the buffer register in the complementary PWM mode the value of the TMGRA0 register TM0 register counting value TMGRD0 register TMGRB0 register TMIOB0 output TMIOD0 output TM 1 TM 1 TM 0 counter value TM 1 counter value configure timing sequence to perform data transmission via CMD0 bit and CMD1 bit while n3 m thus when TM1 register underflows data is tra...

Page 406: ...uffer register in complementary PWM mode has a value of 0000H TM0 register counting value TMGRD0 register TMGRB0 register TMIOB0 output TMIOD0 output when content of TMGRD0 register is 0000H thus when TM0 and TMGRA0 compare matching data is transmitted after that when 0001H n1 m for the very first time thus when TM0 and TMGRA0 compare matching data is transmitted TM 0 counter value TM 1 counter va...

Page 407: ...the value of the buffer register is transmitted to the general purpose register via the timing set by CMD0 bits You cannot directly change from the output of 0 positive phase duty cycle and 100 inverting phase to the output of 100 duty cycle of positive phase and 0 duty cycle of inverting phase ...

Page 408: ...f The source of the forced cutoff EventC event input INTP0 input Event input INTP0 for EVENTC is input to the output of comparator 0 Force the source of the cutoff to be released Stop the counter and release it by software Hardware de software release no need to stop counter Pins that can be forced to cut off Pxx TMIOA0 Pxx TMIOB0 Pxx TMIOC0 Pxx TMIOD0 Pxx TMIOA1 Pxx TMIOB1 Pxx TMI OC1 Pxx TMIOD1 ...

Page 409: ...t can be depressed by software or hardware When forced cutoff the output level can be selected for H level L level and Hi Z Figure 10 68 Block diagram of PWMOP Timer M selector TMIOA0 TMCLK TMIOB0 TMIOC0 TMIOD0 TMIOD1 TMIOC1 TMIOB1 TMIOA1 EVENT C 10 8 2 Registers for PWMOP The registers of the PWMOP are shown in Table 10 21 Table 10 21 Control registers for PWMOP Register name symbol PWMOP control...

Page 410: ...software the forced cutoff is lifted and the pulse output is restored 1 When the HZ_SEL is 1 the forced cutoff is released and the timing of the pulse output recovery is as follows Timer M Complementary PWM mode The edge of TMIOC0 selected by OPEDGE is deforced cutoff the pulse output recovery timer M reset synchronous PWM mode When the count value of TM0 is 0000H the pulse output recovers the abo...

Page 411: ...ted HS_SEL set to 1 There are no limitations when using comparator 0 output and INTP0 input Note 5 Selecting the effective width of the comparator 0 output and the INTP0 input must be greater than one clock cycle Note 6 The count value of TM0 and TM1 0000H refers to the moment when the counter b it15 bit0 is all 0 during the operation of T M0 and TM1 Note 7 If timer M is operating in output compar...

Page 412: ...utoff control 0 0 Disables the forced cutoff feature 0 1 Output Hi Z 1 0 Output L level 1 1 Output H level DFA01 DFA00 TMIOA0 pin output forced cutoff control 0 0 Disables the forced cutoff feature 0 1 Output Hi Z 1 0 Output L level 1 1 Output H level Note 1 The Hi Z output must be selected when the TMIOj0 j A B C D pins are used as PORT outputs and the forced cutoff function is enabled Note 2 The...

Page 413: ...ed cutoff control 0 0 Disables the forced cutoff feature 0 1 Output Hi Z 1 0 Output L level 1 1 Output H level DFA11 DFA10 TMIOA1 pin output forced cutoff control 0 0 Disables the forced cutoff feature 0 1 Output Hi Z 1 0 Output L level 1 1 Output H level Note 1 The Hi Z output must be selected when the TMIOj1 j A B C D pin is used as a PORT output and the forced cutoff function is enabled Note 2 ...

Page 414: ...tion point can be set via the OPEDGE register Figure 10 72 the format of PWMOP edge selection register Address 0x40043C5B after reset 00H R W Symbol 7 6 5 4 3 2 1 0 OPEDGE EG1 EG0 Output force cutoff to dismiss the edge selection 0 0 The rising edge of TMIOC0 is lifted 0 1 The descending edge of TMIOC0 is lifted 1 0 The rising or falling edge of TMIOC0 is lifted 1 1 Do not enable along the selecti...

Page 415: ...MIOC0 TMIOD0 1 Force cutoff state TMIOA0 TMIOB0 TMIOC0 TMIOD0 HZIF0 Output Force Cutoff Source Status Note 1 2 0 The output force cutoff source is within the threshold range 1 The output force cutoff source is out of the threshold range Note 1 Before selecting the INTP0 input by setting the IN_SEL1 IN_SEL0 comparator 0 output as the forced cutoff factor if the output force cutoff source is outside...

Page 416: ...lue of register O PDF0 OPDF1 is output For detailed actions see Figure 10 7 5 The H S_SELbit of theOPCTL0 registers allows you to choose to remove the forced cutoff function by software or hardware 10 8 3 2 Hardware release HS_SEL 0 When timer M works in different modes the de timing is different 1 Outputs outside of complementary PWM functions When timer M operates in output comparison function P...

Page 417: ...orce release mode selection HS_SEL 0 force cut off sourse selection IN_SEL1 0 IN_SEL0 1 input edge selection IN_EG 0 comparator0 output HZIF0 TMIOB0 output TMIOC0 output TMIOD0 output HZOF0 1 When the rising edge of the comparator output signal is detected the TMIOB0 TMIOC0 TMIOD0 pin outputs are forced to cut off 2 After the falling edge of the comparator output signal is detected theHZIF0 bit is...

Page 418: ...imer M Note 2 TMIOC0 output from PWMOP Note 1 TMIOC0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 1 TMIOD0 output from Timer M Note 2 HZOF0 represents cut off state value fixed at H L or Hi Z accordiing to register configuration Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TMIO B D output from Timer M indicates the ...

Page 419: ...sents cut off state value fixed at H L or Hi Z accordiing to register configuration TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOC0 output from PWMOP Note 1 TMIOC0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 1 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TM...

Page 420: ...sents cut off state value fixed at H L or Hi Z accordiing to register configuration TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOC0 output from PWMOP Note 1 TMIOC0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 1 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TM...

Page 421: ...rce release mode selection HS_SEL 0 force cut off sourse selection IN_SEL1 0 INSEL0 1 input edge selection IN_EG 0 comparator0 output HZIF0 TMIOB0 output from PWMOP TMIOD0 output from PWMOP HZOF0 1 When the rising edge of the comparator 0 output signal is detected the output of theT MIOB0 TMIOD0 pin is forced to cut off 2 When the falling edge of the comparator 0 output signal is detected the HZIF...

Page 422: ...IOC0 output from Timer M represents cut off state value fixed at H L or Hi Z accordiing to register configuration TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 1 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TMIO B D output from Timer M indicates...

Page 423: ...HZOF0 represents cut off state value fixed at H L or Hi Z accordiing to register configuration M value of TMGRA0 PWMOP operational clock TIMER M counter0 TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TMIO B D output from Timer M i...

Page 424: ...to register configuration TMIOC0 output from Timer M Comparator 0 output PWMOP operational clock TIMER M counter 1 TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 2 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TMIO B D output from Timer M indicate...

Page 425: ...r Hi Z accordiing to register configuration m value of TMGRA0 PWMOP operational clock TIMER M counter0 Comparator 0 output TMIOB0 output from PWMOP Note 1 TMIOB0 output from Timer M Note 2 TMIOD0 output from PWMOP Note 1 TMIOD0 output from Timer M Note 2 Note 1 The TMIO B D output from PWMOP indicates the state of the pin that reuses the M function of the timer Note 2 TMIO B D output from Timer M ...

Page 426: ...the case of TMIOB0 TMIOC0 TMIOD0 PWMOP operational clock OPCTL0 register select ACT bit comparator0 output HZIF0 TMIOB0 output from PWMOP TMIOD0 output from PWMOP HZOF0 force release mode selection HS_SEL 1 Force cutoff source selection IN_SEL1 0 INSEL0 1 forced cut off release control HZ_REL input edge selection IN_EG 0 TMIOC0 output from PWMOP 1 When the rising edge of the comparator 0 output si...

Page 427: ...e HZ_REL of OPCTL0 to 1 the forced cutoff state can be lifted by signaling from timer M After deregistration HZ_REL is automatically set to 0 When the hardware de cutoff is detected the release is triggered by a signal from timer M and the output is restored When the software is decommissioned theH Z_REL is set to 1 and the release is triggered by the signal of timer M and the output is restored T...

Page 428: ...source selection IN_SEL1 0 INSEL0 1 input edge selection IN_EG 0 comparator0 output HZIF0 TMIOA0 output from PWMOP TMIOA1 output from PWMOP HZOF0 HZOF1 1 When the rising edge of the comparator 0 output signal is detected the output of the TMIOA0 TMIOA1 pin is forced to cut off 2 Set HZ_REL to 1 and wait for each count count value to change to 0000H 3 When the count value of TM0 reaches 0 000H the ...

Page 429: ...off source selection IN_SEL1 0 INSEL0 1 TMIOA0 output from PWMOP TMIOA1 output from PWMOP 1 When the rising edge of the comparator 0 output signal is detected the output of the TMIOA0 TMIOA1 pin is forced to cut off 2 Set HZ_REL to 1 and wait for each count count value to change to 0000H 3 When the count value of TM0 reaches 0 000H the forced cutoff state of T MIOA0 is lifted 4 After the force cut...

Page 430: ...release mode selection HS_SEL 1 Force cutoff source selection IN_SEL1 0 INSEL0 1 input edge selection IN_EG 0 comparator0 output 1 When the rising edge of the comparator 0 output signal is detected the output of the TMIOA0 TMIOA1 pin is forced to cut off 2 Set HZ_REL to 1 and wait for channel 0count count value of timer M to change to 0000H 3 When the count value of TM0 reaches 0000H the forced cu...

Page 431: ...m Timer M Forced cut off release control HZ_REL Forced cut off release mode selection HS_SEL 1 Force cutoff source selection IN_SEL1 0 INSEL0 1 1 When the rising edge of the comparator 0 output signal is detected the output of the TMIOB0 TMIOD0 pins is forced to cut off 2 Set the HZ_REL to 1 and wait for the rising edge of TMIOC0 3 After the rising edge of TMIOC0 is detected the forced cut off sta...

Page 432: ... 1 to allow hazard countermeasures to avoid this risk Note that when using hazard countermeasures the output of timer M is delayed by a clock cycle than when the hazard countermeasure is disabled Figure 10 89 Hazard countermeasure timing diagram PWMOP operational clock force cut off hazard control selection HAZAD_SEL 1 Before TMIOji output Hazard countmeasure After TMIOji output Hazard countmeasur...

Page 433: ...mined If you set OPCTL0 the IN_EG is 0 the high level is the source detected state and the low level is the undetected state If you set OPCTL0 the IN_EG is 1 the low level is the source detected state and the high level is the undetected state Note Before selecting the INTP0 input by setting the IN_SEL1 IN_SEL0 comparator 0 output as the forced cutoff factor if the output force cutoff source is ou...

Page 434: ... TMGRA0 the count value becomes 0000H and the forced cutoff state is lifted 3 Timer M works in reset synchronous PWM mode when the count value reaches the timing of 0 000H Count value 0000H timer M count starts forced cutoff cannot be lifted Timer M in the counting using software to assign the countera value of 0 000H to remove the forced cutoff state In line with the value of TMGRA0 the count val...

Page 435: ...m cn 435 1149 Rev 1 02 Fig 10 91 timing sequence when count value 0000H Count source Fclk 2 timer M count value reaches 0000H at the next cycle counter stop PWMOP operational clock TIMER M counting TMSTR TSTART0 detection signal when TIMER M count 0000H ...

Page 436: ...WMOPEN to 1 2 Set up OPCTL0 register 3 Set OPEDGE register 4 Set OPDF0 OPDF1 register timer M action begins 5 Wait for the forced cutoff state shown by HZOF1 HZOF0 6 force termination Note The PWMOP implements the function of using comparator 0 output external interrupt input INTP0 and Coordination Controllerto force cut off timer M output Therefore the PWMOP must be used when the timer M is activ...

Page 437: ...complementary PWM mode if the PWMOP is in the output forced cut off state the timer M also enters the pulse output forced cut off state which may produce an edge of the de cut off for the PWMOP 3 When using EVENTC as the cutoff source you must use software to deactivate the cutoff state HS_SEL 1 4 When using the output cut off hazard countermeasure the output of the timer M via PWMOP is delayed by...

Page 438: ...me clock consists of the following hardware Table 11 1 Structure of real time clocks Item structure counter Internal counter 16 bits Control registers Perimeter allow register 0 PER0 bit7 Real time clock selection register RTCCL Real time clock control register 0 RTCC0 Real time clock control register 1 RTCC1 Seconds Count Register SEC Minute Count Register MIN Hour Count Register HOUR Day count r...

Page 439: ... minute count regsiter MIN 7 bits second count regsiter SEC 7 bits wait control internal count regsiter 16 bits countig enable disable circuit clock deviation calibration register SUBCUD 8 bits buffer buffer buffer buffer buffer buffer buffer Internal bus selector selector 1 year 1 month 1 day 1 hour 1 minute 1 second 0 5 seconds Note that only the fmx fhoco divider clock after the week 32 768 KHz...

Page 440: ...ster RTCCL Real time clock control register 0 RTCC0 Real time clock control register 1 RTCC1 Second Count Register SEC Minute Count Register MIN Hour Count Register HOUR Day Count Register DAY Week Count Register WEEK Month Count Register MONTH Year Count Register YEAR Clock Error Correction Register SUBCUD Alarm Clock Minute Register ALARMWM Alarm Clock Hour Register ALARMWH Alarm Clock Week Regi...

Page 441: ...d Read and write SFR for real time clock RTC and 15 bit interval timers Note 1 If you want to use a real time clock you must first place the RTCEN position 1 in the oscillation stable state of the counting clock fRTC and then set the following registers When the RTCEN bit is 0 the write operation of the real time clock control register is ignored and the read value is the initial value except for ...

Page 442: ...nting clocks 0 Select the high speed system clock fMX 1 Choose the high speed internal oscillator fhoco RTCCKS1 RTCCKS0 RTCCL6 RTCCL5 Selection of operating clocks for real time clocks 15 bit interval timers for counting clocks 0 0 x x Subsystem clock fSUB 0 1 Low speed internal oscillator clock fIL WUTMMCK0 must be set to 1 1 0 0 1 Master clock fmax fhoco selected via RTCCL7 1952 1 0 0 0 Master c...

Page 443: ...register 1 RTCC1 must be set to 1 It is rewritten later If you change the value of the AMPM bit the value of the hour count register HOUR becomes the corresponding value of the set time system The representation of the time bits is shown in Table 11 2 CT2 CT1 CT0 Choice of Fixed Cycle Interrupt INTRTC 0 0 0 The fixed cycle interrupt feature is not used 0 0 1 0 5 seconds at a time synchronized with...

Page 444: ...pt processing through the interrupt mask flag register And the WAFG flag and RTCIF flag must be cleared after rewriting To set each alarm register RTCC1 register s WALIE flag alarm clock minute register ALARMWM alarm hour register ALARMWH and alarm clock week register ALARMWW the WALL position must be 0 invalid for consistent operation WALIE Operational control of the Alarm Clock Interrupt INTRTC ...

Page 445: ...ter the read write mode of the counter This bit controls the operation of the counter To read and write a count value you must write 1 to this bit Because the internal counter 16 bit continues to run the read and write must end within 1 second and then return to 0 The time required from the RWAIT position 1 to the time the count value can be read and written RWST 1 is up to 1 fRTC clock If an inte...

Page 446: ...elow DVE 0 Period of SEC 00H 20H 40H DVE 1 Period of SEC 00H F12 The setting of the clock error correction value 0 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 1 2 increased 1 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 1 2 Decrease When F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 447: ...e Clock Counters Note If the Write Second Count Register SEC clears the internal counter 16 bits 11 3 7 Minute Count Register MIN This is an 8 bit register that represents the minute count value in 0 to 59 decimal The count is incremented by the overflow of the second counter At write time the data is first written to the buffer and to the counter after passing through up to 2 fRTC clocks The over...

Page 448: ...r 01 12 21 32 If you change the value of the AMPM bit the value of the HOUR register becomes the corresponding value of the time system set Set the HOUR register via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 12H However if the AMPM position is 1 after reset the value of this register becomes 00H Figure 11 8 Format of the Hour Count...

Page 449: ...o clock 07H AM7 o clock 07H 8 o clock 08H AM8 o clock 08H 9 o clock 09H AM9 o clock 09H 10 o clock 10H AM10 o clock 10H 11 o clock 11H AM11 o clock 11H 12 o clock 12H PM12 o clock 32H 13 o clock 13H PM1 o clock 21H 14 o clock 14H PM2 o clock 22H 15 o clock 15H PM3 o clock 23H 16 o clock 16H PM4 o clock 24H 17 o clock 17H PM5 o clock 25H 18 o clock 18H PM6 o clock 26H 19 o clock 19H PM7 o clock 27H...

Page 450: ...e counter after passing through up to 2 fRTC clocks The overflow of the hour count register is ignored during the write operation and is set to the write value The decimal 01 31 must be set in the BCD code Set the DAY register via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 01H Figure 11 9 Format of the Day Count Register DAY Address...

Page 451: ...ing a reset signal the value of this register changes to 00H Figure 11 10 Format of the Week Count Register WEEK Address 0x40044F55H after reset 00HR W Symbol 7 6 5 4 3 2 1 0 WEEK Note 1 The corresponding values of the month count register MONTH and the day count register DAY are not automatically saved to the week register WEEK The following settings must be made after the reset is lifted Week da...

Page 452: ...e steps described in 11 4 3 Reading and Writing to a Real Time Clock Counter 11 3 12 Year Count Register YEAR This is an 8 bit register representing the annual count value from 0 to 99 decimal The count is incremented by the overflow of the month counter MONTH 00 04 08 92 96 are leap years At write time the data is first written to the buffer and to the counter after passing through up to 2 fRTC c...

Page 453: ...value of this register changes to 12H However if the AMPM position is 1 after reset the value of this register becomes 00H Note that the decimal value of 00 23 or 01 12 21 32 must be set in the BCD code If you set a value outside the range the alarm is not detected Figure 11 15 Format of the Alarm Clock Hour Register ALARMWH Address 0x40044F5 BH After reset 12H R W Symbol 7 6 5 4 3 2 1 0 ALARMWH N...

Page 454: ...ryday 11 59 a m 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 Monday to Friday 00 00 pm 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 Sunday 1 30 p m 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 Monday Wednesday Friday 11 59 p m 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 11 3 16 Port mode registers and port registers When using the multiplex port of the RTC1HZ output pin as a 1Hz output the bits of the port mode control register PMCxx the bits of the port ...

Page 455: ...interrupt INTRTC configure second count register configure minute count register configure hour count register configure week count register configure day count register configure month count register configure year count register configure clock deviation calibration register clear interrupt request flag Ifxx clear interrupt mask flag MKxx configure start counting Concentrate 1 The RTCEN position...

Page 456: ...r the RWATCH position 1 is placed the RWAIT position is changed to 1 and the RWST bit is confirmed by polling Then place the RWAIT position 0 and confirm again by polling that the RWST bit becomes 0 and then move to sleep mode reference Fig 11 20 example 2 Figure 11 20 transfers the sleep deep sleep mode steps after the RTCE set to 1 RTCE 1 at least wait for 2 fRTC clock cycles execute WFI instruc...

Page 457: ...ear counter stop operating enter into read write mode of counter confirm counter wait state Read second count register Read minute count register Read hour count register Read week count register read day count register read month count register read year count register configure counter operation RWST 1 No Yes Note That the RWST bit must be confirmed to be 0 before moving to sleep mode Note that ...

Page 458: ... year count register configure counter operation RWST 1 No Yes Note You must confirm that the RWST bit is 0 before moving to SLEEP mode Note 1 Processing from RWAIT position 1 to RWAIT position 0 must be carried out within 1 second 2 To rewrite SEC MIN HOUR WEEK DAY MONTH in counter operation RTCE 1 When the YEAR register is registered it must be overwritten after the INRTC is set to disable inter...

Page 459: ...minute register configure alarm hour register configure alarm week register alarm alignment operation valid INTRTC 1 No Yes detect alarm alignment No fixed cycle interrupt processing Note 1 There is no limit to the order of write operations for alarm minute registers ALARMWM alarm hour registers ALARMWH and alarm clock week registers ALARMWW 2 Fixed cycle interrupts and alarm clock consistent inte...

Page 460: ...ut Start RTCE 0 设定SEC Configure Port RCLOE1 1 RTCE 1 start output from RTC1HZ pin configure to stop counting set Pxx and PMxx to 0 allow RTC1HZ pin output 1Hz configure start counting Note 1 The RTCEN position 1 must first be placed in the oscillation stable state of the counting clock fSUB 2 Some packages do not support the 1Hz output function of real time clocks ...

Page 461: ...e Oscillation Frequency Target Frequency 1 32768 60 Note The correction value is a clock error correction value calculated based on the value of bit12 0 of the clock error correction register SUBCUD Case of F12 0 Correction value F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 1 2 Case of F12 1 Correction F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 1 2 When F12 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 no correction of cl...

Page 462: ... the target frequency is 32768Hz 32767 4Hz 18 3ppm and DEV 1 A formula for calculating the correction value when the DEV bit is 1 is applied Correction value 1 minute correction count value oscillation frequency target frequency 1 32768 60 32767 4 32768 1 32768 60 36 Calculation of the setting value of F12 F0 In the case of a correction value 36 Because the correction value is less than 0 faster F...

Page 463: ...he 15 bit interval timer The 15 bit interval timer consists of the following hardware Table 12 1 Structure of the 15 bit interval timer item structure counter 1 5 bit counter Control registers Peripheral enable register 0 PER0 Real time clock selection register RTCCL 1Control Register ITMC for 5 bit interval timers Figure 12 1 Block diagram of a 15 bit interval timer selector counting clock interr...

Page 464: ...t in use To use the 15 bit interval timer bit7 RTCEN must be set to 1 Set the PER0 register with 8 bit memory manipulation instructions After generating a reset signal the value of this register becomes 00H Figure 12 2 The format of Peripheral enable register0 PER0 Address 0x40020420 After reset 00H R W symbol 7 6 5 4 3 2 1 0 PER0 RTCEN ADCEN IICA0EN SCI1EN SCI0EN CAN0IN TM40EN RTCEN Provides cont...

Page 465: ...t count clocks 0 Select the high speed system clock fMX 1 Select the high speed internal oscillator fhoco RTCCKS1 RTCCKS0 RTCCL6 RTCCL5 Selection of operating clocks for real time clocks 15 bit interval timers for counting clocks 0 0 x x Subsystem clock fSUB 0 1 Low speed internal oscillator clock fIL WUTMMCK0 must be set to 1 1 0 0 1 Master clock fmax fhoco selected via RTCCL7 1952 1 0 0 0 Master...

Page 466: ...4 ITCMP0 is 0 001H or 7FFFH ITCMP14 ITCMP0 0001H counting clock fSUB 32 768kHz 1 32 768 kHz 1 1 0 06103515625 ms 61 03 us ITCMP14 ITCMP0 7FFFH counting clock fSUB 32 768kHz 1 32 768 kHz 32767 1 1000 ms note 1 To change the RINTE bit from 1 to 0 it must be rewritten after the INTIT is set to disable interrupt processing through the interrupt mask flag register To restart the run from 0 to 1 you mus...

Page 467: ...e 15 bit counter starts counting When the 15 bit count value is the same as the itCMP14 ITCMP0 bits setting value the 15 bit count value is cleared to 0 and the count continues generating an interrupt request signal INTIT The basic operation of the 15 bit interval timer is shown in Figure 12 5 Figure 12 5 Operation sequence of a 15 bit interval timer ITCMP14 ITCMP0 0FFH count clock fSUB 32 768kHz ...

Page 468: ...of 1 count clock is then transferred to sleep mode After the RINTE position 1 confirm that the RINTE bit changes to 1 by polling and then move to sleep mode refer to example1 in the figure below Move to sleep mode after at least 1 counting clock time has elapsed since the RINTE set to 1 refer to Example 2 in the figure below return from sleep mode RINTE 1 RINTE 1 YES NO execute WFI instruction con...

Page 469: ... control register OSMC provided on the subsystem clock is 1 and the CPU is running on the subsystem clock fSUB In SLEEP mode the subsystem clock fSUB cannot be output from the CLKBUZn pin Note n 0 1 Figure 13 1 Block diagram of the clock output buzzer output control circuit Internal Bus clock output selection register 1 CKS1 PCLOE1 0 0 0 CSEL1 CCS12 CCS11 CCS10 pre scaler selector selector 5 3 fMA...

Page 470: ...ters Clock output select register n CKSn Port Mode Register PMmn Port Register Pmn 13 3 control Registers of the clock output buzzer output control circuitry 13 3 1 Clock output select register n CKSn This is a register that enable or disables the output of the clock output pin or buzzer frequency output pin CLKBUZn and sets the output clock The clock output of the CLKBUZn pin is selected through ...

Page 471: ...Hz 1 0 0 0 fSUB 32 768kHz 1 0 0 1 fSUB 2 16 384kHz 1 0 1 0 fSUB 22 8 192kHz 1 0 1 1 fSUB 23 4 096kHz 1 1 0 0 fSUB 24 2 048kHz 1 1 0 1 fSUB 25 1 024kHz 1 1 1 0 fSUB 26 512Hz 1 1 1 1 fSUB 27 256Hz Note The output clock must be used within the range of 16MHz For details please refer to AC Features Note 1 Switching of the output clock must be performed after the output is set to Disable Output PCLOEn ...

Page 472: ...port function of the object channel must be set For details please refer to 2 3 1 Port Mode Register PMxx and 2 3 2 Port Register Pxx When using the multiplex port of the clock output buzzer output pin as the clock output buzzer output the bit of the port mode register PMxx and the position of the port register Pxx corresponding to each port must be used 0 Example When the P140 INTP6 CLKBUZ0 is us...

Page 473: ...e CLKBUZn pin CSELn selects the output frequency output is disabled Place bit7 PCLOEn of the CKSn register at 1 to allow the output of the clock buzzer Note 1 When used as a clock output the control circuit starts or stops the clock output after allowing or disabling one clock after the clock output PCLOEn bit Pulses with narrow widths are not output at this time The timing of the outputs allowed ...

Page 474: ...he reset control flag register RESF to 1 For details on RESF registers refer to Chapter 30 Reset Functions When 75 of the overflow time is reached 1 2fIL interval interrupts can be generated 14 2 Structure of the watchdog timer Watchdog timers consist of the following hardware Table 14 1 watchdog timer Item structure counter Internal counter 17 bits Control registers The Watchdog Timer s Allowed R...

Page 475: ...erflow signal reset output control circuit internal reset signal interval time interval time control circuit count value overflow time x3 4 1 2fIL option bytes 000C0H WDTINT option bytes 000C0H WDCS2 WDCS0 option bytes 000C0H WINDOW1 and WINDOW0 option bytes 000C0H WDTON watchdog timer enable register WDTE circuit detects written value other than ACH into WDTE Internal Bus fIL 26 fIL 216 fIL Note ...

Page 476: ...e register WDTE of the watchdog timer Address 0x40021001 after reset 9AH 1AH Note R W WDTE Note The reset value of the WDTE register varies depending on the setpoint of the WDTON bit of the option byte 000C0H For the watchdog timer to run the WDTON must be placed at the position 1 The setpoint of the WDTON bit The reset value of the WDTE register 0 Disables the counting run of the watchdog timer 1...

Page 477: ...ter changes to 00H Figure 14 3 LOCKUP control register LOCKCTL and the format of its protection register PRCR 1 2 Address 40020405H after reset 01H R W LOCKCTL lockup_rst Configuration of the LOCKUP function 0 LOCKUP does not cause a WDT reset 1 LOCKUP causes the WDT to reset Figure 14 3 LOCKUP control register LOCKCTL and the format of its protection register PRCR 2 2 Address 40020406H After rese...

Page 478: ...re 14 4 WDTCFG configuration register WDTCFG0 1 2 3 Address 40020408H After reset 00HR W WDTCFG0 Address 40020409H After reset 00HR W WDTCFG1 Address 4002040AH after reset 00HR W WDTCFG2 Address 4002040BH After reset 00HR W WDTCFG3 WDTCFG0 WDTCFG1 WDTCFG2 WDTCFG3 Configuration of the watchdog timer function 0x1A 0x2B 0x3C 0x4D The operation of the watchdog timer after reset is determined by the op...

Page 479: ...me after the reset must be performed while the window is open If you write the WDTE register while the window is closed an internal reset signal is generated 5 If you do not write ACH to the WDTE register and exceed the overflow time an internal reset signal is generated An internal reset signal is generated if When a bit manipulation instruction is executed on a WDTE register When writing data ot...

Page 480: ...psed you must consider this situation to set the overflow time 14 4 2 Setting of the watchdog timer overflow timer Set the overflow time of the watchdog timer by bit3 1 WDCS2 WDCS0 of the option byte 000C0H In the event of an overflow an internal reset signal is generated If you write ACH to the watchdog timer s allow register WDTE during window opening before the overflow time the count is cleare...

Page 481: ...TE is written at any time before the overflow time the watchdog timer is cleared and the count is restarted The window opening period that can be set is as follows Table 14 4 Settings during the opening of the watchdog timer window WINDOW1 WINDOW0 Watchdog timer during window opening 0 Disable settings 1 0 75 1 1 100 Note When the bit0 WDSTBYON of the option byte 000C0H is 0 it is independent of t...

Page 482: ...terrupt if you want to run with the X1 oscillation clock and clear the watchdog timer because the watchdog timer is cleared after the oscillation stabilization time has elapsed you must consider this situation to set the overflow time Note Continue counting even after intWDTI is generated continue until ACH is written to the allowed register WDTE of the watchdog timer If you do not write ACH to th...

Page 483: ...ion of each channel can be performed in single shot continuous scan mode Various A D conversion modes are set by the combination of modes described below Trigger mode Software triggered Start the conversion with software operations Hardware triggers no wait mode Start the conversion by detecting hardware triggers Hardware triggers wait mode In the switch standby state of the power supply the power...

Page 484: ...BAT32G1x9 user manual Chapter 15 A D converter www mcu com cn 484 1149 Rev 1 02 Figure15 1 Block Diagram of A D converter ...

Page 485: ... The conversion result compares the upper limit value to set the register R W 00H ADC_BASE 0BH ADNSMP The sample time control register of the A D converter R W 0dH ADC_BASE 0CH ADCR 1 2 bit A D conversion result register R 0 000H ADC_BASE 0EH ADCRH 8 bit A D conversion result register R 00H ADC_BASE 0FH ADTES A D test register R W 00H ADC_BASE 10H ADNDIS Charge discharge control registers for A D ...

Page 486: ...s in a reset state 1 An input clock is provided Can read and write SFR used by A D converters Note1 To set the A D converter you must first set the following registers in the ADCEN bit 1 When the ADCEN bit is 0 the value of the control register of the A D converter is the initial value ignoring the write operation Pin Mode Control Register PMCxx except Mode register 0 ADM0 for A D converters Mode ...

Page 487: ...ng control of the A D voltage comparator Note 2 0 Stop the operation of the A D voltage comparator 1 Enable operation of the A D voltage comparator Note1 For details on FR2 FR0 bit SHT1 SHT0 bit and A D conversion refer to Table15 3 Selection of A D conversion times 1 2 Note2 The A D converter takes 1us settling time to start operating In software triggered mode or hardware triggered no wait mode ...

Page 488: ...onversion mode When writing 0 to the ADCS bit When the 4 channel conversion of the setting ends the 0 is automatically cleared Hardware triggers no wait mode Select a mode Continuous transition mode When writing to the ADCS bit 1 When writing 0 to the ADCS bit Single shot conversion mode When writing 0 to the ADCS bit Scan mode Continuous transition mode When writing 0 to the ADCS bit Single shot ...

Page 489: ...pletes ADCS write 1 Note1 Note1 Note1 In software triggered mode or hardware triggered no wait mode the time to rise from the ADCE bit to the ADCS bit to the ADCS bit needs to be at least 1us TBD to stabilize the internal circuitry Note2 In hardware trigger wait mode the A D power settling time of 1us is guaranteed by design Note 1 When you want to use the hardware trigger wait mode disable the AD...

Page 490: ...f conversion clocks Conversion time 0 0 0 0 0 High speed transform mode fCLK 32 45 ADCLK Number of sample clocks 13 5 ADCLKs 1440 fCLK 0 0 1 fCLK 16 720 fCLK 0 1 0 fCLK 8 360 fCLK 0 1 1 fCLK 4 180 fCLK 1 0 0 fCLK 2 90 fCLK 1 0 1 fCLK 1 45 fCLK 0 0 0 1 1 Low current mode fCLK 32 54 ADCLK Number of sample clocks 1 3 5 ADCLKs 1728 fCLK 0 0 1 fCLK 16 864 fCLK 0 1 0 fCLK 8 432 fCLK 0 1 1 fCLK 4 216 fCL...

Page 491: ...1 fCLK 16 1us 720 fCLK 0 1 0 fCLK 8 1us 360 fCLK 0 1 1 fCLK 4 1us 180 fCLK 1 0 0 fCLK 2 1us 90 fCLK 1 0 1 fCLK 1 1us 45 fCLK 0 0 0 1 1 Low current mode fCLK 32 1us 54 ADCLK Number of sample clocks 1 3 5 ADCLKs 1us 1728 fCLK 0 0 1 fCLK 16 1us 864 fCLK 0 1 0 fCLK 8 1us 432 fCLK 0 1 1 fCLK 4 1us 216 fCLK 1 0 0 fCLK 2 1us 108 fCLK 1 0 1 fCLK 1 1us 54 fCLK Note1 In continuous transition mode the A D po...

Page 492: ...of channels cycled when scanning the pattern 0 0 4 channel sweep 0 1 3 channel sweep 1 0 2 channel sweep other Set Prohibit ADSCM The setting of the A D conversion mode 0 Continuous transition mode 1 Single shot conversion mode ADMODE1 ADMODE0 A D conversion mode 0 0 High speed transform mode 1 1 Low current mode other Prohibit settings Note 1 To rewrite the ADM1 register it must be done in the tr...

Page 493: ... 1 When ADCRRegister ADLLRegisters AREA2orADULTSRegister ADCRRegisters AREA3 an interrupt signal is generated INTAD The range of the interrupt signal INTAD of AREA1 to AREA3 is shown in the following figure CHRDE The A D converter scans the mode when the output of the channel id is enabled 0 When scanning mode the channel number is not identified in the conversion results 1 In scan mode the high f...

Page 494: ...ware trigger mode 0 1 1 0 Hardware triggers no wait mode 1 1 Hardware triggers wait mode ADTRS1 ADTRS0 Selection of hardware trigger signals 0 0 Timer channel 1 counts over or captures the end interrupt signal INTTM01 0 1 The event signal selected by the ELC 1 0 Real time clock interrupt signal INTRTC 1 1 Interval timer interrupt signal INTIT Note 1 To override the ADTRG register it must be done i...

Page 495: ...P21 0 0 0 0 0 0 1 0 ANI2 P22 0 0 0 0 0 0 1 1 ANI3 P23 0 0 0 0 0 1 0 0 ANI4 P24 0 0 0 0 0 1 0 1 ANI5 P25 0 0 0 0 0 1 1 0 ANI6 P26 0 0 0 0 0 1 1 1 ANI7 P27 0 0 0 0 1 0 0 0 ANI8 P11 0 0 0 0 1 0 0 1 ANI9 P10 0 0 0 0 1 0 1 0 ANI10 P03 0 0 0 0 1 0 1 1 ANI11 P02 0 0 0 0 1 1 0 0 ANI12 P147 0 0 0 0 1 1 0 1 ANI13 P04 0 0 0 0 1 1 1 0 ANI14 P120 0 0 0 0 1 1 1 1 ANI15 P146 0 0 0 1 0 0 0 0 ANI16 P100 0 0 0 1 0 ...

Page 496: ...NI7 ANI8 ANI9 0 0 0 1 1 1 ANI7 ANI8 ANI9 ANI10 0 0 1 0 0 0 ANI8 ANI9 ANI10 ANI11 0 0 1 0 0 1 ANI9 ANI10 ANI11 ANI12 0 0 1 0 1 0 ANI10 ANI11 ANI12 ANI13 0 0 1 0 1 1 ANI11 ANI12 ANI13 ANI14 0 0 1 1 0 0 ANI12 ANI13 ANI14 ANI15 Other than the above Prohibit settings 3 channel scan mode ADM1 ADMD 1 ADISS ADS 4 0 Analog input channel Scan 0 Scan 1 Scan 2 1 b0 5 h00 ANI0 ANI1 ANI2 1 b0 5 h01 ANI1 ANI2 AN...

Page 497: ...fied as the analog input by the ADS 3 Pins that are set to digital inputs outputs by pin mode control registers PMCxx cannot be set through ADS registers 4 To override the ADISS bit it must be done in the transition stop state ADCS 0 ADCE 0 5 When USing AVREFP as the positive reference voltage for an A D converter ANI0 cannot be selected as the A D conversion channel 6 When USing AVREFM as the neg...

Page 498: ...the A D is not saved Conversion results Figure15 10 Format of the 12 bit A D Conversion Result Register ADCR Reset value 0000H R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCR ADCH3 ADCH2 ADCH1 ADCH0 ADCR 11 0 Note 1 If only 8 bit resolution A D conversion results are required the high 8 bits of the conversion result can be read through the ADCRH register 2 When 16 bits of access are made to the ADCR ...

Page 499: ...ignal the value of this register changes to 00H Note If the value of the A D conversion result is not within the set value range of the A D conversion result comparison function set by the ADRCK bit and the ADUL ADLL register the A D is not saved Conversion results Figure15 11 8 bit A D conversion result register ADCRH Reset value 00H R 7 6 5 4 3 2 1 0 ADCRH Note The conversion results must be rea...

Page 500: ...s the format of the upper limit setting register ADUL Reset Value FFH R W 7 6 5 4 3 2 1 0 ADULTS ADUL7 AOFL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0 15 2 10 The conversion results compare the lower limit value set register ADLL This is the setting register used to check the lower limit value of the A D conversion result The A D conversion result is compared to the value of the ADLL register and the AD...

Page 501: ...5 5 5 ADCLKs 8 h06 6 5 ADCLKs 8 h07 7 5 ADCLKs 8 h08 8 5 ADCLKs 8 h09 9 5 ADCLKs 8 h0a 10 5 ADCLKs 8 h0b 11 5 ADCLKs 8 h0c 12 5 ADCLKs 8 h0d 13 5 ADCLKs The default value 8 h0e 14 5 ADCLKs 8 h0f 15 5 ADCLKs 8 h10 16 5 ADCLKs 8 h11 17 5 ADCLKs 8 h12 18 5 ADCLKs 8 h13 19 5 ADCLKs 8 h14 20 5 ADCLKs 8 hff 255 5 ADCLKs Note To override the ADSMP register it must be done in the transition stop state ADC...

Page 502: ...this register changes to 00H Figure15 15 A D Sampling Time Extension Register ADSMPWAIT Reset value 00H R W 7 6 5 4 3 2 1 0 ADSMPWAIT 0 0 0 0 0 0 0 ADSMPWAIT ADSMPWAIT A D conversion object 0 At 0 the A D sampling time is set directly by the ADSMP register 1 The A D sampling time is arbitrarily extended when 1 and when the sampling time is changed from 1 to 0 the sampling time is controlled by ADS...

Page 503: ...operation instruction After generating a reset signal the value of this register changes to 00H Figure15 16 A D Test Register ADTES Reset value 00H R W 7 6 5 4 3 2 1 0 ADTEST 0 0 0 0 ADTES3 ADTES2 ADTES1 ADTES0 ADTES2 ADTES1 ADTES0 A D operating mode 0 0 0 Usually converted 0 0 1 Self diagnostic test of 0 yards 0 1 1 Half code self diagnostic test 1 0 1 Full code self diagnostic test Other than th...

Page 504: ... not end in single conversion mode 1 In single stroke conversion mode the conversion ends zero is automatically cleared after 2 ADCLKs The ADFLG4 remains at 1 b0 in continuous conversion mode ADFLG3 A D transition status 0 1 ADCLK before the end of the non A D conversion 1 1 ADCLK before the end of A D conversion 1 ADCLK is automatically cleared after 1 ADCLK ADFLG2 A D transition status 0 2 ADCLK...

Page 505: ...ignal the value of this register changes to 00H Figure15 18 A D Charge and Discharge Control Register ADNDIS Reset value 00HW 7 6 5 4 3 2 1 0 ADNDIS 0 0 0 ADNDIS4 ADNDIS3 ADNDIS2 ADNDIS1 ADNDIS0 ADNDIS 4 Charge and discharge control 1 b0 discharge 1 b1 charge ADNDIS 3 0 Charge and discharge time 4 b0000 No charge or discharge is performed 4 b0010 2 ADCLKs 4 b0011 3 ADCLKs 4 b0100 4 ADCLKs 4 b0101 ...

Page 506: ...t pins Control registers PIN Mode Control Registers PMCxx for pin function multiplexing with the analog inputs of the A D converter must be set For details please refer to 2 3 8 pin mode control register PMCxx When using the ANIx pins as analog inputs to A D converters the corresponding pin mode control register PMCxx must be placed at position 1 ...

Page 507: ...lationship INT A function that returns the integer portion of a numeric value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR The value of the A D conversion result register ADCR SAR Successive approximation registers The analog input voltage and the A D conversion result are shown in the following figure Figure15 19 Analog input voltage vs A D conversion result Note AVREF is...

Page 508: ...e ADS registers are overwritten or rewritten during the conversion process the current A D conversion is immediately aborted and the analog inputs reassigned by the ADS registers are A D converted The A D conversion does not start even if the input hardware triggers during the conversion process If the ADCS position is 0 during the conversion the current A D conversion is immediately aborted and t...

Page 509: ...nt A D conversion is immediately aborted and the analog inputs reassigned by the ADS registers are A D converted If the ADCS position is 0 during the conversion the current A D conversion is immediately aborted and then enters the A D conversion standby state If the ADCE position is 0 in the A D conversion standby state the A D converter enters the stopped state When the ADCE bit is 0 even the ADC...

Page 510: ...tten or rewritten during the conversion process the current A D conversion is immediately aborted and then A D is performed from the initial channel re specified by the ADS registers The A D conversion does not start even if the input hardware triggers during the conversion process If the ADCS position is 0 during the conversion the current A D conversion is immediately aborted and then enters the...

Page 511: ...egister is overwritten or rewritten during the conversion process the current A D conversion is immediately aborted and the A D conversion is performed from the initial channel re specified by the ADS register If the ADCS position is 0 during the conversion the current A D conversion is immediately aborted and then enters the A D conversion standby state If the ADCE position is 0 in the A D conver...

Page 512: ... A D conversion is immediately aborted and the analog inputs reassigned by the ADS registers are A D converted If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion restarts If the ADCS position is 0 during the conversion the current A D conversion is immediately aborted and then enters the A D conversion standby state ...

Page 513: ...e current A D conversion is immediately aborted and the analog inputs reassigned by the ADS registers are A D converted If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion restarts If the ADCS position is 0 during the conversion the current A D conversion stops immediately and then enters the A D transition standby st...

Page 514: ... process the current A D conversion is immediately aborted and then A D is performed from the channel reassigned by the ADS registers If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion starts again from the original channel If the ADCS position is 0 during the conversion the current A D conversion is immediately abor...

Page 515: ... during the conversion process the current A D conversion is immediately aborted and the A D conversion is performed from the initial channel re specified by the ADS register If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion starts again from the original channel If the ADCS position is 0 during the conversion the c...

Page 516: ...ed and the analog inputs reassigned by the ADS registers are A D converted If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion restarts If the ADCS position is 0 during the conversion the current A D conversion is aborted immediately then the hardware triggers the standby state and the A D converter enters the stopped...

Page 517: ...signed by the ADS registers are A D converted If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion restarts If the ADCS position is 0 during the conversion the current A D conversion is aborted immediately then the hardware triggers the standby state and the A D converter enters the stopped state When the ADCE bit is 0...

Page 518: ...mediately aborted and the scan conversion starts with the channel re specified by the ADS registers If you rewrite 1 for the ADCS bit during the conversion process the current A D conversion is immediately aborted and the conversion starts again from the original channel If the ADCS position is 0 during the conversion the current A D conversion is aborted immediately then the hardware triggers the...

Page 519: ... aborted and the scan conversion begins with the channel reassigned by the ADS register If you rewrite 1 for the ADCS bit during the conversion the current A D conversion is immediately aborted and the conversion is scanned starting from the initial channel If the ADCS position is 0 during the conversion the current A D conversion is aborted immediately then the hardware triggers the standby state...

Page 520: ...n single conversion ADMD bit selection mode Scan mode ADTRG register ADTMD1 bit ADTMD0 bit configure as software trigger mode ADM2 register ADREFP bit ADREFM bit Select reference voltage ADRCK bit select compare range of A D conversion result which generates interrupt signal ADNSMP register configure sampling time ADUL ADLL register configure A D conversion result comparision upper and lower limit...

Page 521: ... configure as hardware trigger zero wait mode ADTRS1 bit ADTRS0 bit select trigger source ADM2 register ADREFP bit ADREFM bit Select reference voltage ADRCKbit select compare range of A D conversion result which generates interrupt signal ADNSMP register configure sampling time ADUL ADLL register configure A D conversion result comparision upper and lower limit ADS register select analog input cha...

Page 522: ...Configure as Hardware trigger wait mode ADTRS1 bit ADTRS0 bit select trigger source ADM2 register ADREFP bit ADREFM bit Select reference voltage ADRCK bit select compare range of A D conversion result which generates interrupt signal configure sampling time ADUL ADLL register configure A D conversion result comparision upper and lower limit ADS register select analog input channel set ADCE bit of ...

Page 523: ...re as single conversion mode ADTRG register ADTMD1 bit ADTMD0 bit configure as software trigger mode ADM2 register ADREFP bit ADREFM bit Select P20 AVREFP P21 AVREFM as reference voltage ADS register select temperature sensor output voltage or internal reference voltage set ADCS bit of ADM0 register to 1 enter into hardware trigger standby state set ADCS bit of ADM0 register to 1m start A D conver...

Page 524: ... FR0 bit configure A D conversion time ADM1 register ADSCM bit continous conversion single conversion ADMD bit selection mode mode ADTRG register ADTMD1 bit ADTMD0 bit configure as software trigger mode ADM2 register ADREFP bit ADREFM bit Select reference voltage ADNSMP register configure sampling time ADS register Turn off all analog input channels ADTES register ADTES1 bit ADTES0 bit select VSS ...

Page 525: ...n 8 bit resolution converter that converts a digital input to an analog signal and can control the analog output of 2 channels ANO0 ANO1 The D A converter has the following functions 8 bit resolution 2ch R 2R trapezoidal mode Analog output voltage 8 bit resolution VDDm8 256 m8 the value set for the DACSi register Operating mode Usual mode Real time output mode Note i 0 1 ...

Page 526: ...A converter write DACS0 register DAMD0 DAM internal bus internal bus D A conversion value configuration register0 DACS0 ELCREQ0 VSS pin VDD pin ANO0 pin ANO1 pin DACE0 DAM DACE1 DAM Write DACS1 register DAMD1 DAM ELCREQ1 D A conversion value configuration register1 DACS1 D A convertor mode register DAM selector selector Note ELCREQ0 and ELCREQ1 are trigger signals for real time output mode event s...

Page 527: ...to 1 The PER1 register is set via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 00H Figure 16 2 format of Peripheral enable register 1 PER1 Address 0x4002081A after reset 00H R W symbol PER1 DACEN Control of the input clock of the D A converter 0 Stop providing the input clock Cannot write SFR used by D A converters The D A converter i...

Page 528: ...n value sets register i DACSi i 0 1 This is the register that sets the analog voltage value output to the ANO0 pin and the ANO1 pin when using the D A converter The DACSi registers are set via the 8 bit memory operation instructions After generating a reset signal the value of these registers changes to 00H Figure 16 4 The D A conversion value sets the format of register i DACSi i 0 1 Address 4004...

Page 529: ...gister n ELSELRn n 00 21 16 3 5 Registers that control the function of the analog input pin port Control registers port mode register PMxx and port mode control register PMC for port function multiplexing with the analog output of the D A converter must be set For details please refer to 2 3 1 Port Mode Register PMxx and 2 3 6 Port Mode Control Register PMCxx When using the ANO0 pin and the ANO1 p...

Page 530: ... D A conversion value setting register i The above 1 4 is the initial setting Place the DACEi position of the DAM register 1 allow D A conversion Start the D A conversion and output the analog voltage set by 4 to the ANOi pin after the settling time has elapsed Thereafter when you want to perform a D A conversion write the DACSi register Hold the results of the previous D A conversion before perfo...

Page 531: ...igger signal for the real time output mode the D A conversion begins and after a settling time has elapsed the analog voltage set by 4 is output to the ANOi pin Before performing the next D A conversion which generates a trigger signal for real time output mode set the analog voltage value of the ANOi pin output to the DACSi registers The analog voltage value of the ANOi pin output must be set to ...

Page 532: ...egister write enable ELC timing signal i Enable in GC D A conversion timing sequence DACSi register ANOi data latches Data 0 Data 0 Data 1 Data 1 Data 2 Data 2 Note i 0 1 Usual operating mode and real time output mode where conversion is not allowed Write the data latch output from the ANOi pin after writing the DACSi register 1 cycle running clock Real time output mode where conversion is allowed...

Page 533: ...it and the DAMDi position 0 Place the DACEN position of the PER1 register 0 stop after placing the DACEi bit and the DAMDi position 0 DAC If the DACEN position is 0 all registers inside the DAC are cleared Therefore when running again each SFR needs to be set 4 When D A conversion is allowed A D conversion cannot be performed on analog input pins that are multiplexed with the AN0 pin and the ANO1 ...

Page 534: ...d internal reference voltage 1 45V for CMP0 Selectable external pin inputs 4 on the negative side of CMP1 internal reference voltage and internal reference voltage 1 45V for CMP1 Programmable internal reference voltage on the negative side 256steps The positive end of CMP0 selects the output of the PGA Selectable External Pin Inputs on the Positive Side of CMP1 4 When the positive input voltage th...

Page 535: ...0 CMP 0 选择器 A D convertor CMP0SEL VCIN0 选择器 VREF0 internal reference voltage 1 45V noise removal Digital filter C0ENB C0FCK C0EPO C0EDG Edge detection circuit output inversion circuit C0IE CMP0 interrupt CMP0 EVENTC event VCOUT0 选择器 VDD AVREFP comparator reference voltage use D A convertor VREF0 选择器 VSS AVREF M CVRVS0 CVRVS1 CVRE0 C0VRS 7 0 C0REFS1 C0REFS0 C0OE C0MON C0OP selector selector...

Page 536: ...oval Digital filter C1ENB C1FCK C1EPO C1EDG Edge detection circuit output inversion circuit C1IE CMP1 interrupt CMP1 EVENTC event VCOUT1 选择器 VDD AVREFP comparator reference voltage use D A convertor VREF1 选择器 VSS AVREF M CVRVS0 CVRVS1 CVRE1 C1VRS 7 0 C1REFS 2 0 C1OE C1OP VCIN11 VCIN12 VCIN13 C1MON C1TWMD general timer unit TO02 signal selector selector selector selector ...

Page 537: ...er control registers COMPFIR Comparator output control registers COMPOCR The comparator built in reference control register CVRCTL The comparator built in reference voltage selection register of 0 C0RVM Comparator built in reference voltage selection register1 C1RVM Comparator 0 input selection control register CMPSEL0 The comparator 1 input selection control register CMPSEL1 Comparator 0 hysteres...

Page 538: ...o 00H Figure 17 3 format of the Peripheral enable register 1 PER1 Address 0x4002081A after reset 00H R W symbol PER1 PGACMPEN Control of the comparator input clock 0 Stop providing the input clock Cannot write SFR used by the comparator The comparator is in reset state 1 An input clock is provided I can read and write the SFR used by the comparator note To set the comparator you must first place t...

Page 539: ...on After generating a reset signal the value of this register changes to 00H Figure 17 4 Comparator Mode Setting Register COMPMDR Format Address 400438after 40H reset 00H R W symbol COMPMDR C1MON Monitor flags for comparator 1 note 1 2 0 VCIN1 comparator1of the reference voltage or comparator1Stop running 1 VCIN1 the reference voltage of comparator 1 C1ENB Comparator 1 runs allowed 0 Disables the ...

Page 540: ... detection of comparator 0 C0EPO Comparator 0 edge polarity toggle note 2 0 An interrupt request is generated through the rising edge of comparator 0 1 An interrupt request is generated through the falling edge of comparator 0 C0FCK1 C0FCK0 Comparator 0 filter selection note 2 0 0 Comparator 0 does not have a filter 0 1 Comparator 0 has a filter that samples via fCLK 1 0 Comparator 0 has a filter ...

Page 541: ... 1 02 If you change the C0FCK1 C0FCK0 bits from 00B comparator 0 without filter to another value comparator 0 has a filter you must pass before updating the output of the filter After 4 samples use the interrupt request of comparator 0 or the event signal output to EVENTC ...

Page 542: ...er COMPOCR Format Address 40043842H after reset 00H R W Symbol 7 6 5 4 3 2 1 0 COMPOCR C1OTWMD Comparator 1 s TIMER WINDOW output mode controls bit note1 0 Comparator 1 normal output mode controlled by C1OE 1 Comparator 1TIMER WINDOW output mode controlled by TO02 and C1OE together C1OP The choice of polarity of the VCOUT1 output 0 Output from VCOUT1 comparator 1 1 Inverting output from VCOUT1 com...

Page 543: ...ent may be generated Override this bit after setting the EVENTC s ELSELR20 register to 0 not linking to the output of comparator 0 Also initialize the IF bit of the interrupt request flag register no interrupt request after rewriting the C0OE bit Note5 Set the C0OE bit C0OP bit and input the result of comparator 9 into the PWM option unit to control the forced cutoff of the PWM output Note6 If C1I...

Page 544: ...tage 1 1 Enable operation of the built in reference voltage 1 CVRVSN The base side selection bit of the built in reference voltage 0 Vss is selected at the ground end of the built in reference voltage 1 The base end of the built in reference voltage selects AVREFM Note 1 CVRE0 Built in control bit of reference voltage 0 0 Disables operation of the built in reference voltage 0 1 Enable operation of...

Page 545: ...00H Figure 17 8 Comparator with the format of the built in reference voltage selection register i CiRVM Address 400438434H C0RVM 400438435H C1RVM reset 00H R W Symbol 7 6 5 4 3 2 1 0 CiRVM CiRV S7 CiRV S6 CiRV S5 CiRV S4 CiRV S3 CiRV S2 CiRV S1 CiRV S0 The comparator s built in reference voltage is set 0 0 0 0 0 0 0 0 AVREFP or VDD 256 x0 0 0 0 0 0 0 0 1 AVREFP or VDD 256 x1 0 0 0 0 0 0 1 0 AVREFP...

Page 546: ...er generating a reset signal the value of this register changes to 00H Figure 17 9 The format of input signal selection of Comparator 0 control register CMPSEL0 Address 4004384AH after reset 00H R W Symbol 7 6 5 4 3 2 1 0 CMPSEL0 CMP0SEL The positive input signal selection bit of comparator 0 0 Select an external pin VCIN0 pin 1 Select the PGA output signal C0REFS1 C0REFS0 The negative input signa...

Page 547: ...SEL1 CMP1SEL0 The positive input signal selection bit of comparator 1 0 0 Select an external pin VCIN10 pin 0 1 Select the external pin VCIN11 pin 1 0 Select the external pin VCIN12 pin 1 1 Select the external pin VCIN13 pin C0REFS2 C0REFS1 C0REFS0 The negative input signal selection bit of comparator 1 0 0 0 Select the built in reference voltage VREF1 0 0 1 Select the internal reference voltage 1...

Page 548: ...ion instruction After generating a reset signal the value of this register changes to 00H Figure 17 1 Format of the hysteresis control register CMP0HY of comparator 0 Address 4004384EH after reset 00H R W Symbol 7 6 5 4 3 2 1 0 CMP0HY C0HYSVS1 C0HYSVS0 The hysteresis voltage selection bit of comparator 0 0 0 No lag 0 1 20mV 1 0 40mV 1 1 60mV C0HYSLS1 C0HYSLS0 The hysteresis mode of comparator 0 se...

Page 549: ... instruction After generating a reset signal the value of this register changes to 00H Figure 17 2 Format of the hysteresis control register CMP1HY of the 2 comparator 1 Address 4004384FH after reset 00H R W Symbol 7 6 5 4 3 2 1 0 CMP1HY C1HYSVS1 C1HYSVS0 The hysteresis voltage selection bit of comparator 1 0 0 No lag 0 1 20mV 1 0 40mV 1 1 60mV C1HYSLS1 C1HYSLS0 Comparator 1 s hysteresis mode sele...

Page 550: ...t be used for each port and the position of the port control register PMCxx is 1 When using the VCOUT0 and VCOUT1 functions control registers for port functions that are multiplexed with the object channel port mode registers PMxx and port registers Pxx and peripheral IO redirect registers Pxx must be set PIOR2 PIOR3 For details please refer to 2 3 1 Port Mode Register PMxx 2 3 2 Port Register Pxx...

Page 551: ... analog input functions PMCxx The VCIN0 pin VCi and IVREFi pins feature selection with PMCxx position 1 analog input Place PMxx at 1 input mode 12 COMPMDR CiENB 1 allowed to run 13 Wait for the settling time of the comparator min 3μs 14 COMPFIR CiFCK With or without a digital filter select the sample clock CiEOP CiEDG Select the edge detection condition for the interrupt request rising falling or ...

Page 552: ...quests refer to 17 4 2 Comparator i Interrupt i 0 1 Figure 17 11 Comparator i i 0 1 is an example of operation basic mode basic mode operation example reference input voltage IVREFi or BGRVRREF in low speed mode reducing power consumption by prolong the delay time of input decision result in high speed mode increasing power consumption by shorten the delay time of output decision result CiMON bit ...

Page 553: ...nterrupt operation example sample timing sequence CiMON CMPIFi bit of interrupt control register set to 0 via program as long as 1 out of 3 times the signal is not identical the signnal will be discarded as noise CMPIFi bit remain unchanged if 3 times signals are identical then it is considered as signal change and CMPIFi bit change to 1 Note that the CiFCK1 CiFCK0 bits of the COMFIR register abov...

Page 554: ... as long as 1 out of 3 times the signal is not identical the signnal will be discarded as noise output remain unchanged if 3 times signals are identical then it is considered as signal change and reflected to output when input signal of digital filter changes output single trigger pulse directly output the input singal of digital filter inverted output of the input singal of digital filter when in...

Page 555: ...egister 1 PER1 it must be set as follows Place the CiENB position of the COMMDR register 0 stop the comparisonr from running Place the interrupt request flag register at IF position 0 clear the unneeded interrupt before the comparator stops Place the PGACMPEN position of the PER1 register 0 If the clock is stopped by setting the PER1 register the internal registers of the comparator are all initia...

Page 556: ...functions There are 7 options for amplification gain per PGA 4x 8x 10x 12x 14x 16x 32x An external pin can be selected as ground for the PGA negative side feedback resistor with PGA0 defaulting to differential mode and PGA1 defaulting to single ended mode The output of PGA 0 can be selected as an analog input for the A D converter or as an analog input on the positive end of comparator 0 CMP0 The ...

Page 557: ...BAT32G1x9 user manual Chapter 18 Programmable Gain Amplifier PGA www mcu com cn 557 1149 Rev 1 02 18 2 Structure of a programmable gain amplifier Figure18 1 diagram of a programmable gain amplifier ...

Page 558: ...s to 00H Figure18 2 The format of the Peripheral enable register 1 PER1 Reset value 00H R W 7 6 5 4 3 2 1 0 PER1 DACEN TIMERBEN PGACMPEN TIMERMEN DTCEN PWMOPEN TIMERCEN TIMERAEN PGACMPEN Control of the input clock of the comparator programmable gain amplifier 0 Stop providing the input clock The registers of the comparator or programmable gain amplifier are not writable comparators or the programm...

Page 559: ...hoice of feedback resistor ground PVRVSNote PGA0 PGA1 0 Select the PGAnGND pin default Select Vss default 1 Select Vss Select the PGAnGND pin PGAnVG2 PGAnVG1 PGAnVG0 PGAn gain 0 0 0 4 times 0 0 1 8 times 0 1 0 10 times 0 1 1 12 times 1 0 0 14 times 1 0 1 16 times 1 1 0 32 times other Set Prohibit Note PGA0 defaults to select the PGA0GND pin as the feedback resistor ground which is differential mod...

Page 560: ...x 10x 12x 14x 16x 32x The amplified voltage can be used for the analog input of the A D converter and the positive input signal of comparator 0 CMP 0 The steps to start and stop the programmable gain amplifier are as follows 18 4 1 The start up procedure for the programmable gain amplifier Taking PGA0 as an example the setup steps are as follows Note 1 Setting the PGAEN bit to 1 requiresaPGA settl...

Page 561: ...ogrammable gain amplifier Taking PGA0 as an example the setup steps are as follows Note 1 When restarting PGA and A D conversion or amplifier a PGA settling time of 1 0 us is required after setting the PGAEN bit to 1 2 Even if the PGA operation is stopped the straight through pin can be used for A D conversion and comparator action ...

Page 562: ...tion assignments for each channel supported by this product are as follows unit passage Used as SSPI Used as a UART Used as a simple I2C 0 0 SSPI00 Support slave selection input function UART0 IIC00 1 SSPI01 IIC01 2 SSPI10 UART1 IIC10 3 SSPI11 IIC11 1 0 SSPI20 UART2 IIC20 1 SSPI21 IIC21 2 0 SSPI30 UART3 IIC30 1 SSPI31 IIC31 When using UART0 for channels 0 and 1 of unit 0 SSPI00 and SSPI01 cannot b...

Page 563: ...pecific setup examples refer to 19 53 wire serial I O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI20 SSPI20 SSPI20 Operation of SSPI21 SSPI30 SSPI31 communication Sending and receiving data 7 bit or 8 bit data length SCI0 Data length of 7 16 bits SCI1 and SCI2 Phase control of sending and receiving data MSB LSB preferred Clock Control Master or Slave selection Phase control of input output clocks Set t...

Page 564: ...achieved by using two channels dedicated for transmit even channel and receive dedicated odd channel For a specific setup example please refer to 19 7Operation of UART UART0 UART3 communication Sending and receiving data 7 bit 8 bit or 9 bit data length SCI0 7 bit 8 bit 9 bit or 16 bit data lengths SCI1 and SCI2 MSB LSB preferred Level setting of sending and receiving data selection of inverted ph...

Page 565: ...IC21 IIC30 IIC31 communication communications Sending and receiving data Master send master receive limited to single master function ACK output function note ACK detection function 8 bits data length when sending an address specify the address with a high 7 bits and R W control with the lowest bit Manual generation of start conditions and stop conditions Interrupt function End of transfer interru...

Page 566: ...able register 0 2 PER0 2 Serial clock selection register m SPSm Serial channel enable status register m SEm Serial channel start register m SSm Serial channel stop register m STm Serial output enable register m SOEm Serial output register m SOm Serial output level register m SOLm Input Switch Control Register ISC Noise filter enable register 0 NFEN0 register for each channel section Serial data re...

Page 567: ...ol circuit serail flag clean trigger register00 SIR00 fMC K When SSPI00 SCLK00 when IIC00 SCL00 serial clock input output pin SSPI01 SCLK01 IIC01 SCL01 serial clock input output pin channel1 support LIN bus serial data input pins SSPI01 SDI01 IIC01 SDA01 SSPI10 SCLK10 IIC10 SCL10 serial clock input output pin serial data Input pins SSPI10 SDI10 IIC10 SDA10 UART0 RxD1 SSPI11 SCLK11 IIC11 SCL11 seri...

Page 568: ...t latch Pxx SNFEN20 serial communication operation configuration register 10 SCR10 serial status register 00 SSR00 error message Clean up error control circuit interrupt control circuit output control circuit output latch Pxx PMxx serial data output pin SSPI20时 SDO20 IIC20时 SDA20 UART2时 TxD2 mode selection SSPI20 or IIC20 or UART2 used as transmission communication control circuit serail flag clea...

Page 569: ...gister is set to 8 bits low or 9 bits low Regardless of the output order of the data bit0 and bit1 DLSmn0 DLSmn1 of the set register mn SCRmn are run according to serial communication settings save to the low 8 bits or low 9 bits data as follows 7 bits of data length bit0 6 saved in the SDRmn register 8 bits of data length bit0 7 saved in the SDRmn register 9 bits of data length bit0 8 saved in th...

Page 570: ...al data register mn SDRmn mn 00 01 10 11 After reset 0000H R W 40041211H in the case of SDR00 40041310H in the case of SDR00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 8 7 6 5 4 3 2 1 0 Shift register Note For the high 7 bit function of the SDRmn register refer to 19 3 Registers for Controlling Universal Serial Communication Units ...

Page 571: ...erred to the shift register is set to the serial data register SDRmn Regardless of the output order of the data bit3 to bit 0 DLSmn3 of the set register mn SCRmn is run according to the serial communication DLSmn0 settings the data saved to the SDRmn register is as follows 7 bits of data length bit0 6 saved in the SDRmn register 8 bits of data length bit0 7 saved in the SDRmn register 16 bit data ...

Page 572: ...e 19 4 Serial data register mn SDRmn mn 20 21 30 31 format After reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Shift register Note For the high 7 bit function of the SDRmn register refer to 19 3 Registers for Controlling Universal Serial Communication Units ...

Page 573: ...nel start register 0 R W 0000H SCI0 22H ST0 Serial channel stop register 0 R W 0000H SCI0 24H SPS0 Serial clock selection register 0 R W 0000H SCI0 26H SO0 Serial output register 0 R W 0F0FH SCI0 28H SOE0 The serial output enable register 0 R W 0000H SCI0 2AH SOL0 Serial output level register 0 R W 0000H SCI0 34H SDR00 01 02 03 Serial data register 00 01 02 03 R W 0000H SCI0 210H 212H 214H 216H SS...

Page 574: ...able status register 2 R W 0000H SCI2 10H SS2 Serial channel start register 2 R W 0000H SCI2 12H ST2 Serial channel stop register 2 R W 0000H SCI2 14H SPS2 Serial clock selection register 2 R W 0000H ICS2 16H SO2 Serial output register 2 R W 0303O CLOCK SCI2 18H SOE2 The serial output enable register 2 R W 0000H SCI2 1AH SOL2 Serial output level register 2 R W 0000H SCI2 20H SDR20 21 Serial data r...

Page 575: ...munication unit m the following registers must first be set in the SCImEN bit 1 When the SCImEN bit is 0 the write operation of the control register of the universal serial communication unit m is ignored and the read values are initial values input switching control register ISC Noise filter enable register 0 NFEN0 port input mode register PIMx port output mode register POMx Except for the port m...

Page 576: ...rial clock selection register m SPSm After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPSm PRSmk3 PRSmk2 PRSmk1 PRSmk0 Select note for the running clock CKmk 0 0 0 0 fCLK 0 0 0 1 fCLK 2 0 0 1 0 fCLK 22 0 0 1 1 fCLK 23 0 1 0 0 fCLK 24 0 1 0 1 fCLK 25 0 1 1 0 fCLK 26 0 1 1 1 fCLK 27 1 0 0 0 fCLK 28 1 0 0 1 fCLK 29 1 0 1 0 fCLK 210 1 0 1 1 fCLK 211 1 1 0 0 fCLK 212 1 1 0 1 fCLK 213 ...

Page 577: ... edge detection circuitry By setting the CCSmn bit and the SDRmn register 7 bits high a transmit clock fTCLK is generated CCSmn Channel n transmission clock fTCLK selection 0 The CKSmn bit specifies the running clock fMCK s divider clock 1 Input clock fSCLK from the SCLKp pin slave transfer in SSPI mode The transmit clock fTCLK is used for shift registers communication control circuits output cont...

Page 578: ... mode 0 1 UART mode 1 0 Simple I2C mode 1 1 Disable settings MDmn0 Channel n interrupt source selection 0 The end of transfer is interrupted 1 Buffer null interrupt Occurs when data is transferred from the SDRmn register to the shift register On consecutive sends if the MDmn0 bit is 1 and the data for SDRmn is empty write down the next send data Note 1 Limited to SMR01 SMR03 SMR11 registers Note t...

Page 579: ... SDIp input timing sequence SCLKp SDOp SDIp input timing sequence data and clock phase selection in SSPI mode in UART mode and simple I2C mode must set DAPmn bit and CKPmn bit both to 0 Type EOCmn Mask control of error interrupt signals INTSREx x 0 3 0 Disables the generation of error interrupts INTSREx generate INTSRx 1 Enable intSREx to be interrupted by errors INTSRx is not generated when an er...

Page 580: ...top bit length 1 bit 1 0 Stop bit length 2 bits mn 00 02 10 20 1 1 Disable settings If an end of transmit interrupt is selected an interrupt occurs after all stop bits have been transmitted At UART reception or in simple I2C mode it must be set to 1 stop bit SLCmn1 SLCmn0 0 1 In SSPI mode it must be set to no stop bit SLCmn1 SLCmn0 0 0 When the UART is transmitted it must be set to 1 bit SLCmn1 SL...

Page 581: ...the SDRmn register 〇 1 1 0 0 13 bits of data length bit0 to 12 saved in the SDRmn register 〇 1 1 0 1 14 bit data length bit0 to 13 stored in the SDRmn register 〇 1 1 1 0 15 bits of data length bit0 to 14 saved in the SDRmn register 〇 1 1 1 1 16 bit data length bit0 to 15 stored in the SDRmn register 〇〇 other Prohibit settings In the simple I2C mode DLSmn3 DLSmn0 0111B must be set Note 1 Limited t...

Page 582: ...in 16 bit increments However the high 7 bits can only be read and written when the run stops SEmn 0 In operation SEmn 1 only the low 8 bits or 9 bits lower of the SDRmn register can be written and the high of the SDRmn register is 7 The read value of the bit is always 0 After generating the reset signal the value of the SDRmn register changes to 0000H Figure 19 8 serial data register mn SDRmn Afte...

Page 583: ...e of the SDRmn register changes to 0000H Figure 19 9 serial data register mn SDRmn After reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn SDRmn 15 9 Run the transmit clock setting for clock division 0 0 0 0 0 0 0 fMCK 0 0 0 0 0 0 1 fMCK 2 0 0 0 0 0 1 0 fMCK 3 0 0 0 0 0 1 1 fMCK 4 1 1 1 1 1 1 0 fMCK 127 1 1 1 1 1 1 1 fMCK 128 Note 1 When the operation stops SEmn 0 bit8 0 must be cleared ...

Page 584: ...After generating a reset signal the value of the SIRmn register changes to 0000H Figure 19 10 serial flag clears the format of the trigger register mn SIRmn After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRmn FECTmn Note 1 Clearing of the channel n frame error flag is triggered 0 Do not clear 1 Clear the FEFmn bit of the SSRmn register to 0 PECTmn Channel n parity error flag c...

Page 585: ... placed at SSm position 1 Communication Standby time When the communication ends Set Condition When communication begins BFFmn The status representation flag of the channel n buffer register 0 The SDRmn register does not hold valid data 1 The SDRmn register holds valid data Clear Condition When the transmit data from the SDRmn register to the shift register is completed during the send process Whe...

Page 586: ...d of the UART reception parity error When the I2C is sent and when the ACK receives the timing slave does not return an ACK signal ACK not detected OVFmn Channel n overflow error detection flag 0 No errors occurred 1 An error occurred Clear Condition When writing 1 to the OVCTmn bit of the SIRmn register Set Condition In the state where the RXEmn bit of the SCRmn register is 1 receive mode transmi...

Page 587: ...8 7 6 5 4 3 2 1 0 SS0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS1 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS2 SSmn The trigger for channel n run start 0 No triggering 1 Place the SEmn position 1 and transfer to the Communication Standby note Note If you place the SSmn position 1 during communication the communication is stopped and enters the s...

Page 588: ...he value of the STm register changes to 0000H Figure 19 13 serial channel stop register m STm After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST1 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST2 STmn Channel n runs to stop triggering 0 No triggering 1 Clear the SEmn bit to 0 and stop the...

Page 589: ... register can be set by software and output from the serial clock pin Thus arbitrary waveforms such as start conditions or stop conditions can be generated by software Read the SEm registers via 16 bit memory manipulation instructions It can read the lower 8 bits of the SEm register with SEmL and through the 8 bit memory operation instruction After generating a reset signal the value of the SEm re...

Page 590: ... is set by the 16 bit memory operation instruction I can set the low 8 bits of the SOEm register with SOEmL and through the 8 bit memory operation instruction After generating a reset signal the value of the SOEm register changes to 0000H Figure 19 15 the format of serial output enable register m SOEm After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOE0 After reset 0000HR W Symb...

Page 591: ...nction such as a port function the corresponding CKOmn bit and SOmn position 1 must be placed The SOm registers are set via 16 bit memory operation instructions After generating a reset signal the value of the SOm register changes to 0F0FH Figure 19 16 the format of serial output register m SOm After reset 0F0FH R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO0 After reset 0303HR W Symbol 15 14...

Page 592: ... the low 8 bits of the SDOLm register with SOLmL and through the 8 bit memory operation instruction After generating a reset signal the value of the SOLm register changes to 0000H Figure 19 17 format of serial output level register m SOLm After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOL0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOL1 After reset 0000H...

Page 593: ...an example of the level reversal of the transmitted data is shown in Figure 19 18 Figure 19 18 Example of level inversion of the transmitted data a Non inverting output SOLmn 0 SOLmn 0 output TxDq b phase inverting output SOLmn 0 SOLmn 1 output TxDq transmit data transmit data inverted phase Note m Unit number m 0 2 n Channel number n 0 2 ...

Page 594: ...rial clock is input During the period when the SS00 pin is input low if a serial clock is input it is sent and received according to the settings of each mode The ISC register is set by the 8 bit memory operation instruction After generating a reset signal the value of the ISC register changes to 00H Figure 19 19 Format of input switching control register ISC After reset 00H R W Symbol 7 6 5 4 3 2...

Page 595: ...to 00H Figure 19 20 the format of noise filter enable register 0 NFEN0 After reset 00H R W Symbol 7 6 5 4 3 2 1 0 NFEN0 SNFEN30 RxD 3 pin noise filter is used or not 0 Noise filter OFF 1 Noise filter ON When used as the RxD3 pin SNFEN3 0 must be placed at position 1 When used as a function other than the RxD3 pin SNFEN30 must be placed at position 0 SNFEN20 The RxD2 pin is used or not for noise fi...

Page 596: ... of the port mode register PMxx must be 0 and the position of the port register Pxx 1 must be used for each port In addition when used for N channel open drain output mode the position of the port output mode register POMxx corresponding to each port must be 1 Example P02 is used as a serial data output in case the port mode controls register 0 at PMC02 position 0 Place the PM02 position 0 of port...

Page 597: ...sable clocks to each peripheral hardware Reduce power consumption and noise by stopping clocks to unused hardware To stop universal serial communication unit 0 the bit2 SCI0EN of PER0 must be set to 0 To stop Universal Serial Communication Unit 1 the bit3 SCI1EN of PER0 mustbe set to 0 To stop Universal Serial Communication Unit 2 bit3 SCI2EN of PER2 mustbe placed at 0 Note 1 When the SCImEN bit i...

Page 598: ...The serial output enable register m SOEm This is the register that sets the output of serial communication that enable or stops each channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOEm 0 Stops the output by running through serial communication For channels that have stopped serial output the value of the SOMn bit of the SOm register can be set by software d Serial output register m SOm This is the ...

Page 599: ... internal counter of the channel Maximum transfer rate note Master communication Max fCLK 2 Slave communication Max fMCK 6 Interrupt function Transmit end interrupt buffer empty interrupt Error Detection Flag Overflow error Note must be used within the range that satisfies the SCLK Cycle Time tKCY characteristics Please refer to the data sheet for details Channels 0 to 3 for SCI0 channels 0 to 1 f...

Page 600: ...1 Selectable end of transmit interrupt single pass mode or buffer empty interrupt continuous transfer mode Error detection flags not The length of the transferred data SCI0 7 or 8 bits SCI1 SCI2 7 16bit Transfer Rate Note Max fCLK 2 Hz Min fCLK 2 215 128 Hz fCLK System clock frequency Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial cl...

Page 601: ... selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers when clock phase is positive phase CKPmn of SCRmn register as 0 1 means starting communication when clock phase is inverted phase CKPmn 1 0 means star...

Page 602: ...port mode register target channel data output and clock output are valid set SSmn bit of target channel to 1 Semn 1 set as operation enable state complete initial configuration If transmit data to SIOp register bit 7 0 of SDRmn register then communcation starts Figure 19 24 The abort step of the master transmission termination configuration starts TSFmn 0 write into STm register modify SOEm regist...

Page 603: ...gister mn modify SMRmn register configuration modify SCRmn register configuration modify SOEm register configuration modify SOm register configuration modify SOEm register configuration selection selection selection mandatory configure port write into SSm register configure port register and port mode register set target channel data output and clock output to be valid set SSmn bit of target chann...

Page 604: ...end mode type 1 DAPmn 0 CKPmn 0 SCLKp pin SDOp pin INTSSPIp shift register mn TSFmn SDRmn SEmn STmn SSmn transmit data1 transmit data1 transmit data2 transmit data2 transmit data3 transmit data3 shift operation shift operation shift operation transmit data transmit data transmit data Remark m unit number m 0 2 n channel number n 0 3 p SSPI number p 00 01 10 11 20 21 30 31 mn 00 03 10 11 20 21 ...

Page 605: ...uest flag IFxx and release interrupt mask MKxx output SDOp and SCLKp signal start communication via writing into SIOp if there are data to be transmitted then read transmit data from reserved region and write into SIOp update transmit data pointer Else set communication completion flag to 1 SCI initial configuration transmission completion interrupt transmit next data write transmit data into SIOp...

Page 606: ...it data1 transmit data2 transmit data2 transmit data3 transmit data3 Note If the BFFmn bit of the serial status register mn SSRmn is 1 when valid data is saved in the serial data register mn SDRmn is given When the SDRmn register writes the transmit data it rewrites the send data Note that the MDmn0 bit of the serial mode register mn SMRmn can be rewritten even in operation However in order to cat...

Page 607: ...ad transmit data from reserved region and write into SIOp To update the transmit data pointer and the number of transmit data clear the MDmn bit when the MDmn bit is 1 Otherwise the communication is terminated SCI initial configuration buffer empty transmit completion interrupt communication data count 0 write transmit data into SIOp SDRmn 7 0 RETURN transmission completes disable interrupt mask s...

Page 608: ...iscontinuity continuous transfer mode Error detection flag Only the overflow error detection flag OVFmn length of transmit data SCI0 7 or 8 bits SCI1 SCI2 7 16 bit Transfer Rate Note Max fCLK 2 Hz Min fCLK 2 215 128 Hz fCLK system clock frequency data phase Can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Start the data output when the serial clock starts running DAPmn 1 The data out...

Page 609: ...ration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers when clock phase is positive phase CKPmn of SCRmn register as 0 1 means starting communication when clock phase is inverted phase CKPmn 1 0 means starting communication SIOp baud rate configuration operation clock fmck scaling configuration recei...

Page 610: ... channel to valid SSmn bit of target channel set to 1 Semn 1 set to operation enable state Wait for master device clock complete initial configuration Communication starts when dummy data is set in the SIOp register bit7 0 of the SDRmn register Figure 19 32 The abort step of the master receive termination configuration starts TSFmn 0 write into STm register modify SOEm register configuration modif...

Page 611: ...ifying serial communcation operation configuration register mn modify SMRmn register configuration modify SCRmn register configuration modify SOm register configuration clear error flag selection selection selection Configure port write SSm register via Configure port register and port mode register set data output and clock output of target channel to valid SSmn bit of target channel set to 1 Sem...

Page 612: ...ft register mn TSFmn SDRmn SEmn STmn SSmn virtual data used for receiving virtual data virtual data Receiving shift operation Receiving shift operation1 data reception data reception data reception1 data reception2 data reception3 Receiving shift operation data reception data reception1 data reception2 data reception3 Read Write Read Write Read Write Remark m unit number m 0 2 n channel number n 0...

Page 613: ... internal RAM reserved region transmit data pointer communication data count after clear interrupt request flag Ifxx and release interrupt mask MKxx enable interrupt output SCLKp signal start communicating via writing into SIOp read received data and write into storage region update receive data pointer and communication data count SCI initial configuration transmission completion interrupt read r...

Page 614: ...data reception2 data reception data reception data reception Receiving shift operation data reception1 Receiving shift operation Receiving shift operation Read Write Read Read Write Write Note that the MDmn0 bit can be rewritten even during operation However in order to catch up with the end of transmission interruption of the last received data it must be rewritten before the last bit can be rece...

Page 615: ...t SCLKp signal start communicating via writing into SIOp if there are data to be received read the data and write into storage region update receive data pointer communication data count 1 SCI initial configuration buffer empty transmit completion interrupt BFFmn 1 read receiving data to SIOp SDRmn 7 0 RETURN communication data count 0 disable interrupt mask write STmn bit to 1 communication compl...

Page 616: ...ose between an end of transmit interrupt single pass mode or a buffer null interrupt continuous transfer mode Error detection flags There is only the overflow error detection flag OVFmn The length of the transferred data SCI0 7 or 8 bits SCI1 SCI2 7 16bit Transfer Rate Note Max fCLK 2 Hz Mi n fCLK 2 215 128 Hz fCLK System clock frequency Data phase It can be selected by the DAPmn bit of the SCRmn ...

Page 617: ...rform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers when clock phase is positive phase CKPmn of SCRmn register as 0 1 means starting communication when clock phase is inverted phase CKPmn 1 0 means starting communication SIOp baud rate configuration ...

Page 618: ...t register and port mode register target channel data output and clock output are valid set SSmn bit of target channel to 1 Semn 1 set as operation enable state complete initial configuration If transmit data to SIOp register bit 7 0 of SDRmn register then communcation starts Figure 19 40 Abort steps of the master transmit and receive termination configuration starts TSFmn 0 write into STm registe...

Page 619: ...odifying serail mode register mn configuration re configure when modifying serial communcation operation configuration register mn modify SMRmn register configuration modify SCRmn register configuration modify SOEm register configuration modify SOm register configuration modify SOEm register configuration selection selection selection selection configure port write into SSm register via Configure ...

Page 620: ...n STmn SSmn SDOp pin data reception1 data reception2 data reception3 Receiving shift operation Receiving shift operation Receiving shift operation data reception1 data reception2 data reception3 Read Write Read Write Write transmit data1 transmit data 2 transmit data 3 transmit data1 transmit data 2 transmit data 3 data transmission and reception data transmission and reception data transmission a...

Page 621: ...e region transmit data pointer communnication data count after clear interrupt request flag Ifxx and release interrupt mask MKxx enable interrupt output SDOp and SCLKp signal start communication via writing into SIOp read received data and write into storage region update receive data pointer SCI initial configuration transmission completion interrupt read received data into SIOp SDRmn 7 0 RETURN ...

Page 622: ...Receiving shift operation Write Write Read Write Read Read Write Write Note1 Note2 Note2 Note 1 If the BFFmn bit of serial status register mn SSRmn is 1 during the period valid data is saved in serial data register mn SDRmn when writing transmit data to the SDRmn register rewrite the send data 2 If the SDRmn register is read during this period the data can be read and sent At this point the transf...

Page 623: ...ead data from storage region and write into SIOp update storage pointer If transmit completes communication data count 1 then modify bit of transmit completion interrupt SCI initial configuration buffer empty transmit completion interrupt BFFmn 1 read receiving data to SIOp SDRmn 7 0 RETURN communication data count 0 disable interrupt mask set STmn bit to 1 communication completed Yes No No Yes ma...

Page 624: ...transfer mode Error detection flags There are only overflow error detection flags OVFmn The length of the transferred data SCI0 7 or 8 bits SCI1 SCI2 7 to 16 bits Transfer rate Max fMCK 6 Hz note1 2 Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial clock starts running DAPmn 1 Starts the data output half a clock before the serial clock ...

Page 625: ...data transmit sequence selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers SIOp baud rate configuration configuration of transmit data Note Note This example is the setting method for SCI0 The data lengt...

Page 626: ... mode register set data output of target channel to valid set SSmn bit of target channel to 1 set to enable operation state complete initial configuration If transmit data to SIOp register bit 7 0 of SDRmn register wait for master device clock Figure 19 48 Abort step of the slave send termination configuration starts TSFmn 0 write into STm register modify SOEm register configuration modify SOm reg...

Page 627: ... register configuration modify SOEm register configuration port operation write into SSm register via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state restart configuration completes set SOEmn bit to 0 stop output of target channel configure serial data Somn initial output voltag...

Page 628: ...mode type 1 DAPmn 0 CKPmn 0 SCLKp pin SDOp pin INTSSPIp shift register mn TSFmn SDRmn SEmn STmn SSmn transmit data1 transmit data2 transmit data3 transmit data1 transmit data2 transmit data3 shift operation shift operation shift operation transmit data transmit data transmit data Remark m unit number m 0 2 n channel number n 0 3 p SSPI number p 00 01 10 11 20 21 30 31 mn 00 03 10 11 20 21 ...

Page 629: ...d internal RAM storage region transmit data pointer communnication data count after clear interrupt request flag Ifxx and release interrupt mask MKxx enable interrupt start communication via clock provided by master device clear interrupt request flag Ifxx SCI initial configuration transmission completion interrupt RETURN continue transmitting disable interrupt mask set STmn bit to 1 communcation ...

Page 630: ... data3 shift operation shift operation shift operation transmit data transmit data transmit data Note Note If the BFFmn bit of the serial status register mn SSRmn is 1 when valid data is saved in the serial data register mn SDRmn is given When the SDRmn register writes the transmit data it rewrites the send data Note that the MDmn0 bit of the serial mode register mn SMRmn can be rewritten even in ...

Page 631: ...d write into SIOp update storage pointer Else changes interrupt to transmission completion SCI initial configuration buffer empty transmit completion interrupt communication data count 1 write transmit data into SIOp SDRmn 7 0 RETURN communication data count 1 disable interrupt mask set STmn bit to 1 communication completed write MDmn 0 bit to 0 Yes No No Yes main program interrupt process program...

Page 632: ...re are only overflow error detection flags OVFmn The length of the transferred data SCI0 7 or 8 bits SCI1 SCI2 7 to 16 bits Transfer rate Max fMCK 6 Hz note1 2 Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial clock starts running DAPmn 1 Starts the data output half a clock before the serial clock starts running Clock phase It can be se...

Page 633: ...transmit sequence selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers SIOp baud rate configuration received data Note Note This example is the setting method for SCI0 The data length of SCI1 SCI2 and the...

Page 634: ...ort register and port mode register data input and clock input of target channel is set to valid SSmn bit of target channel set to 1 Semn 1 set to operation enable state Wait for master device clock Figure 19 56 Abort step of Slave reception termination configuration starts TSFmn 0 write into STm register modify SOEm register configuration configure PER0 register termination configuration ends Yes...

Page 635: ...peration configuration register mn modify SMRmn register configuration modify SCRmn register configuration port operation write into SSm register via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state wait for master device clock restart configuration completes clear error flag whe...

Page 636: ... 0 SCLKp pin SDIp pin INTSSPIp shift register mn TSFmn SDRmn SEmn STmn SSmn data reception1 data reception2 data reception3 data reception1 data reception2 data reception data reception3 data reception data reception Receiving shift operation Receiving shift operation Receiving shift operation Read Read Read Remark m Cell number m 0 2 n Channel number n 0 3 p SSPI number p 00 01 10 11 20 21 30 31 ...

Page 637: ...ge region receiving data pointer and receiving data count enable interrupt after clear interrupt request flag Ifxx and release interrupt mask MKxx start communication via clock provided by master device read received data and write into storage region perform inccremental counting to receiving data count update receiving data count SCI initial configuration transmission completion interrupt read r...

Page 638: ...errupt continuous transfer mode Error detection flags There are only overflow error detection flags OVFmn The length of the transferred data SCI0 7 or 8 bits SCI1 SCI2 7 to 16 digits Transfer rate Max fMCK 6 Hz Note1 2 Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data input output when the serial clock starts running DAPmn 1 Starts data input output half a cl...

Page 639: ...orm LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers SIOp Note baud rate configuration configuration of transmit data received data register Note This example is the setting method for SCI0 The data length of SCI1 SCI2 and the serial data register SDRmn...

Page 640: ...erial communication unit from reset state start providing clock configure operational clock configure operational mode etc configure communication format set baud rate bit15 9 to 0000000B configure serial data Somn initial output voltage set SOEmn bit to 1 enable data output of target channel via Configure port register and port mode register set data output of target channel to valid set SSmn bit...

Page 641: ...figuration ends Yes No if there are ongoing data transmission then wait till transmission completed if need urgent stop then no need to wait set STmm bit of target channel to 1 SEmn 0 set to operation stop state set SOEmn bit to 0 stop output of target channel when emergency stop based on needs modify serial data SOmn voltage level of the target channel stop clock of universal serial communication...

Page 642: ...ster via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state restart configuration completes set SOEmn bit to 0 stop output of target channel set SOEmn bit to 0 stop output of target channel set SOEmn bit to 1 enable target channel data otuput clear error flag when OVF flag remains ...

Page 643: ...mn SSmn SDIp pin transmit data1 transmit data 2 transmit data 3 data reception1 data reception2 data reception3 data reception1 data reception2 data reception3 Receiving shift operation Receiving shift operation Receiving shift operation transmit data1 transmit data 2 transmit data 3 data transmission and reception data transmission and reception data transmission and reception Read Write Write Re...

Page 644: ... flag Ifxx and release interrupt mask MKxx enable interrupt start communication via clock provided by master device SCI initial configuration transmission completion interrupt RETURN transmit and receive next data disable interrupt mask set STmn bit to 1 communication completed No Yes main program interrupt process program main program if interrupt generated via transmission completion jump to int...

Page 645: ...ta transmission and reception Read Write Read Read Write Write Note1 Note2 Note2 Note 1 If the BFFmn bit of serial status register mn SSRmn is 1 during the period valid data is saved in serial data register mn SDRmn when writing and sending data to the SDRmn memory rewrite the send data 2 If the SDRmn register is read during this period the data can be read and sent At this point the transfer run ...

Page 646: ...ial configuration buffer empty transmit completion interrupt BFFmn 1 read receiving data to SIOp SDRmn 7 0 RETURN communication data count 0 disable interrupt mask set STmn bit to 1 communication completed Yes No No Yes main program interrupt process program main program if buffer empty or transmit completion interrupt occurs jump to interrupt process program communication data count 1 continue co...

Page 647: ... equation 1 Master device 2 Slaves Note The maximum allowable transmit clock frequency is fMCK 6 Note Because the value of SDRmn 15 9 is the value of bit15 9 of the serial data register mn SDRmn 1111111B so it is 0 127 The operating clock fMCK depends on bit15 of the serial clock selection register m SPSm and the serial mode register mn SMRmn CKSmn Transmit clock frequency Object Channel s operati...

Page 648: ... 1 fCLK 213 3 91kHz X X X X 1 1 1 0 fCLK 214 1 95kHz X X X X 1 1 1 1 fCLK 215 977Hz 1 0 0 0 0 X X X X fCLK 32MHz 0 0 0 1 X X X X fCLK 2 16MHz 0 0 1 0 X X X X fCLK 22 8MHz 0 0 1 1 X X X X fCLK 23 4MHz 0 1 0 0 X X X X fCLK 24 2MHz 0 1 0 1 X X X X fCLK 25 1MHz 0 1 1 0 X X X X fCLK 26 500kHz 0 1 1 1 X X X X fCLK 27 250kHz 1 0 0 0 X X X X fCLK 28 125kHz 1 0 0 1 X X X X fCLK 29 62 5kHz 1 0 1 0 X X X X f...

Page 649: ...overflow error occurs software operation Hardware Status Comments Read the serial data The BFFmn bit of the SSRmn register is 0 and the channel n is in a receiver state This is to prevent an overflow error from occurring to end the next receipt during error handling Read the serial status register mn SSRmn The type of error is determined and the read value is used to clear the error flag Clear tri...

Page 650: ...a MSB LSB preferred Level setting for sending and receiving data Clock Control Phase control of input output clocks Set the transmission period generated by the prescaler and the internal counter of the channel Maximum transfer rate note Slave communication Max fMCK 6 Interrupt function Transmit end interrupt buffer empty interrupt Error Detection Flag Overflow error Note must be used within the r...

Page 651: ...communication object the SDO pin can communicate data to the master device When a slave is not selected as the communication object the SDO pin becomes a high level output so in an environment where multiple slaves are connected the SDO pin needs to be set to Nch O D and the node pulled up In addition even the serial clock entered into the master device is not transmitted and received Note the Sla...

Page 652: ...output data is synchronized shifted with the falling edge of the serial clock and the data is received synchronously with the rising edge SSmn SDOmn sample timing sequence SDImn SCLKmn CKPmn 0 SSEmn TSFmn BFFmn configure transmit data DAPmn 1 When the DAPmn bit is 1 if the data is sent when SSmn is set to be high the initial data bit7 is provided to the data output However even the rising edge of ...

Page 653: ...2 Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial clock starts running DAPmn 1 Starts the data output half a clock before the serial clock starts running Clock phase It can be selected by the CKPmn bit of the SCRmn register CKPmn 0 Normal phase CKPmn 1 Inverted Data direction MSB priority or LSB priority Slave selection input function...

Page 654: ...ler output clock CKm0 1 SPSm register configured pre scaler output clock CKm1 interrupt source of channel n 0 Transmit completion interrupt 1 Buffer empty interrupt data transmit sequence selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal...

Page 655: ...et channel to 1 g input switch control register ISC This is controlled by SS00 pin of SSPI00 slave channel channel 0 of unit 0 0 SS00 pin input invalid 1 SS00 pin input valid Note 1 m Unit number m 0 n Channel number n 0 p SSPI number p 00 2 Fixed setting in SSPI Slave send mode Cannot be set initial value is set This is a bit that cannot be used in this mode and the initial value is set if it is ...

Page 656: ...eset state start providing clock configure operational clock configure operational mode etc configure communication format set baud rate bit15 9 to 0000000B configure serial data Somn initial output voltage set SOEmn bit to 1 enable data output of target channel via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 set to ...

Page 657: ...to 1 SEmn 0 set to operation stop state set SOEmn bit to 0 stop output of target channel when emergency stop based on needs modify serial data SOmn voltage level of the target channel stop clock of universal serial communication unit set to reset state finish termination configuration enter into next processing selection mandatory mandatory selection selection Note m Unit number m 0 n Channel numb...

Page 658: ...configuration modify SOEm register configuration modify SOm register configuration modify SOEm register configuration port operation write into SSm register via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state restart configuration completes set SOEmn bit to 0 stop output of targ...

Page 659: ...pe 1 DAPmn 0 CKPmn 0 SCLKp pin SDOp pin INTSSPIp shift register mn TSFmn SDRmn SEmn STmn SSmn SSp pin transmit data1 transmit data 2 transmit data 3 transmit data1 transmit data 2 transmit data 3 transmit data1 transmit data 2 transmit data 3 shift operation shift operation shift operation transmit data transmit data transmit data Note m Unit number m 0 n Channel number n 0 p SSPI number p 00 ...

Page 660: ... communnication data count after clear interrupt request flag Ifxx and release interrupt mask MKxx enable interrupt start communication via clock provided by master device SCI initial configuration transmission completion interrupt RETURN continue transmitting disable interrupt mask set STmn bit to 1 communcation completes No Yes main program interrupt process program main program generate interru...

Page 661: ... data2 transmit data3 transmit data3 transmit data transmit data transmit data shift operation shift operation shift operation Note Note If the BFFmn bit of the serial status register mn SSRmn is 1 when valid data is saved in the serial data register mn SDRmn is given When the SDRmn register writes the transmit data it rewrites the send data Note that the MDmn0 bit of the serial mode register mn S...

Page 662: ...storage pointer Else changes interrupt to transmission completion SCI initial configuration buffer empty transmit completion interrupt communication data count 1 write transmit data into SIOp SDRmn 7 0 RETURN communication data count 1 disable interrupt mask set STmn bit to 1 communication completed write MDmn 0 bit to 0 Yes No No Yes main program interrupt process program main program from reserv...

Page 663: ...e selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial clock starts running DAPmn 1 Starts the data output half a clock before the serial clock starts running Clock phase It can be selected by the CKPmn bit of the SCRmn register CKPmn 0 Normal phase CKPmn 1 Inverted Data direction MSB priority or LSB priority Slave selection input function You can select the r...

Page 664: ...utput clock CKm0 1 SPSm register configured pre scaler output clock CKm1 interrupt source of channel n 0 Transmit completion interrupt1 Buffer empty interrupt data transmit sequence selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal seria...

Page 665: ...rget channel to 1 g input switch control register ISC This is controlled by SS00 pin of SSPI00 slave channel channel 0 of unit 0 0 SS00 pin input invalid 1 SS00 pin input valid Note 1 m Unit number m 0 n Channel number n 0 p SSPI number p 00 2 Fixed setting in Slave receive mode Cannot be set initial value is set This is a bit that cannot be used in this mode and the initial value is set if it is ...

Page 666: ... valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state wait for master device clock write into ISC register set SSIE00 bit to 1 enable channel 0 slave selection function operates Figure 19 82 Abort step of Slave reception termination configuration starts TSFmn 0 write into STm register modify SOm register configuration configure PER0 register termination configuratio...

Page 667: ...e when serial communication operation configuration register mn modify SMRmn register configuration modify SCRmn register configuration port operation write into SSm register via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 Semn 1 configure as operation enable state wait for master device clock restart configuration c...

Page 668: ...pe 1 DAPmn 0 CKPmn 0 SCLKp pin SDIp pin INTSSPI p shift register mn TSFmn SDRmn SEmn STmn SSmn SSp pin transmit data1 transmit data 2 data reception 3 data reception 1 data reception 2 data reception 3 Receiving shift operation Receiving shift operation Receiving shift operation data reception data reception data reception Read Read Read Note m Unit number m 0 n Channel number n 0 p SSPI number p ...

Page 669: ...age region receiving data pointer and receiving data count enable interrupt after clear interrupt request flag Ifxx and release interrupt mask MKxx start communication via clock provided by master device read received data and write into storage region perform inccremental counting to receiving data count update receiving data count SCI initial configuration transmission completion interrupt read ...

Page 670: ...e Max fMCK 6 Hz note1 2 Data phase It can be selected by the DAPmn bit of the SCRmn register DAPmn 0 Starts data output when the serial clock starts running DAPmn 1 Starts the data output half a clock before the serial clock starts running Clock phase It can be selected by the CKPmn bit of the SCRmn register CKPmn 0 Normal phase CKPmn 1 Inverted Data direction MSB priority or LSB priority Slave se...

Page 671: ...output clock CKm1 interrupt source of channel n 0 Transmit completion interrupt 1 Buffer empty interrupt data transmit sequence selection 0 perform MSB first input output 1 perform LSB first input output data length configuration 0 7 bit data length 1 8 bit data length data and clock phase selection details refer to 19 3 control universal serial communication unit registers SIOp baud rate configur...

Page 672: ...r ISC This is controlled by SS00 pin of SSPI00 slave channel channel 0 of unit 0 0 SS00 pin input invalid 1 SS00 pin input valid Note that the SIOp register must be set to send data before the master device starts to output the clock Note 1 m Unit number m 0 n Channel number n 0 p SSPI number p 00 2 Fixed setting in Slave receive mode Cannot be set initial value is set This is a bit that cannot be...

Page 673: ...nication format set baud rate bit15 9 to 0000000B configure serial data Somn initial output voltage set SOEmn bit to 1 enable data output of target channel via Configure port register and port mode register data output of target channel set to valid When connecting to multiple slave devices configure N channel open drain before configure data output set SSmn bit of target channel to 1 SEmn 1 confi...

Page 674: ...re ongoing data transmission then wait till transmission completed if need urgent stop then no need to wait set STmm bit of target channel to 1 SEmn 0 set to operation stop state set SOEmn bit to 0 stop output of target channel when emergency stop based on needs modify serial data SOmn voltage level of the target channel stop clock of universal serial communication unit set to reset state finish t...

Page 675: ...connecting to multiple slave devices configure N channel open drain before configure data output set SSmn bit of target channel to 1 SEmn 1 configure to enable operation state restart configuration completes set SOEmn bit to 0 stop output of target channel configure serial data Somn initial output voltage set SOEmn bit to 1 enable target channel data otuput clear error flag when OVF flag remains a...

Page 676: ...SFmn SDRmn SEmn STmn SSmn SSp pin SDIp pin data reception1 data reception2 data reception3 transmit data1 transmit data 2 transmit data 3 Read Write Read Read Write Write data reception1 data reception2 data reception3 Receiving shift operation Receiving shift operation Receiving shift operation transmit data1 transmit data 2 transmit data 3 data transmission and reception data transmission and re...

Page 677: ...t mask MKxx enable interrupt start communication via clock provided by master device SCI initial configuration transmission completion interrupt RETURN transmit and receive next data disable interrupt mask set STmn bit to 1 communication completed No Yes main program interrupt process program main program if interrupt generated via transmission completion jump to interrupt process program update c...

Page 678: ...d reception Receiving shift operation Receiving shift operation Receiving shift operation Note1 Note2 Note2 Note 1 If the BFFmn bit of serial status register mn SSRmn is 1 during the period valid data is saved in serial data register mn SDRmn when writing transmit data to the SDRmn register rewrite the send data 2 If the SDRmn register is read during this period the data can be read and sent At th...

Page 679: ...mpletion interrupt BFFmn 1 read receiving data to SIOp SDRmn 7 0 RETURN communication data count 0 disable interrupt mask set STmn bit to 1 communication completed Yes No No Yes main program interrupt process program main program if buffer empty or transmit completion interrupt occurs jump to interrupt process program communication data count 1 continue communicating write MDmn 0 bit to 1 communic...

Page 680: ... X X X X 0 0 0 1 fCLK 2 16MHz X X X X 0 0 1 0 fCLK 22 8MHz X X X X 0 0 1 1 fCLK 23 4MHz X X X X 0 1 0 0 fCLK 24 2MHz X X X X 0 1 0 1 fCLK 25 1kHz X X X X 0 1 1 0 fCLK 26 500kHz X X X X 0 1 1 1 fCLK 27 250kHz X X X X 1 0 0 0 fCLK 28 125kHz X X X X 1 0 0 1 fCLK 29 62 5kHz X X X X 1 0 1 0 fCLK 210 31 25kHz X X X X 1 0 1 1 fCLK 211 15 63kHz X X X X 1 1 0 0 fCLK 212 7 81kHz X X X X 1 1 0 1 fCLK 213 3 9...

Page 681: ...e operation Hardware Status Comments Read the serial data register mn SDRmn The BFFmn bit of the SSRmn register is 0 and the channel n is in a receiver state This is to prevent an overflow error from occurring to end the next receipt during error handling next receipt during error handling Read the serial status register mn SSRmn The type of error is determined and the read value is used to clear ...

Page 682: ...ed Additional parity function of parity bits Stop bit attachment stop bit detection function Interrupt function Transmit end interrupt buffer empty interrupt Error interrupts caused by frame errors parity errors and overflow errors Error Detection Flag Frame error parity error overflow error Note Only UART0 supports 9 bits of data length UART0 uses channel 0 and channel 1 of SCI0 UART1 uses CHANNE...

Page 683: ...of the transferred data SCI0 7 digit 8 digit or 9 bit Note 1 SCI1 SCI2 7 to 16 bits Transfer rate Max fMCK 6 bps SDRmn 15 9 2 Min fCLK 2 215 128 bps note2 Data phase Normal phase output default high Inverting output default low Parity bits You can choose from the following No parity bits Additional zero checks Additional parity Additional odd checksum Stop bit You can choose from the following Add...

Page 684: ...ty 10B add even parity 11B add odd parity TXDq 0 positive phase normal transmit 1 inverted phase transmit baud rate configuration transmit data configuration Note2 Note 1 Limited to SCR00 registers other fixed as 1 2 When communicating with a 9 bit data length bit0 to 8 of the SDRm0 register is the setting area for sending data Only UART0 can communicate with a data length of 9 bits Note This exam...

Page 685: ...output value as 0 1 serial data output value as 1 Note Note Note That before starting the transmission when the SOLmn bit of the corresponding channel is 0 1 must be set When the SOLmn bit of the corresponding channel is 1 0 must be set During communication the value changes depending on the communication data Note 1 m Unit number m 0 2 n Channel number n 0 2 q UART number q 0 3 mn 00 02 10 2 0 2 ...

Page 686: ...of target channel set to valid set SSmn bit of target channel to 1 Semn 1 set to operation enable state initial configuration completes Configure transmit data to SDRmn 7 0 TXDq register 8 bits or SDRmn 8 0 register 9 bits start communication Modifing SOLm register configuration configure output data voltage level Figure 19 97 The abort steps sent by the UART termination configuration starts TSFmn...

Page 687: ...odify SOEm register configuration modify SOm register configuration modify SOEm register configuration configure port write into SSm register configure port register and port mode register set target channel data output to be valid set SSmn bit of target channel to 1 Semn 1 set as operation enable state restart configuration completes set SOEmn bit to 0 stop output of target channel configure seri...

Page 688: ...RT send single send mode TxDq pin INTSTq shift register mn TSFmn SDRmn SEmn STmn SSmn transmit data1 transmit data1 transmit data2 transmit data2 transmit data3 transmit data3 shift operation shift operation shift operation transmit data transmit data transmit data Remark m unit number m 0 2 n channel number n 0 2 q UART number q 0 3 mn 00 02 10 20 ...

Page 689: ...equest flag IFxx and release interrupt mask MKxx start transmission via writing into SDRmn 7 0 if there are data to be transmitted then read transmit data from reserved region and write into TxDq update transmit data pointer Else set communication completion flag to 1 SCI initial configuration transmission completion interrupt transmit next data write data into SDRmn 7 0 TxDq regsiter 8 bit or SDR...

Page 690: ...eration transmit data transmit data transmit data Note Note If the BFFmn bit of the serial status register mn SSRmn is 1 when valid data is saved in the serial data register mn SDRmn is given When the SDRmn register writes the transmit data it rewrites the send data Note that the MDmn0 bit of the serial mode register mn SMRmn can be rewritten even in operation However in order to catch the end of ...

Page 691: ...ansmit data from storage region and write into TxDq update transmit data pointer and transmit data count If no data to transmit then clear MDmn bit while MDmn bit is 1 Else complete transmission SCI initial configuration buffer empty transmit completion interrupt communication data count 0 write data into SDRmn 7 0 TxDq regsiter 8 bit or SDRmn 8 0 9 bits RETURN transmission completes disable inter...

Page 692: ...r detection flags Frame Error Detection Flag FEFmn Parity Error Detection Flag PEFmn Overflow Error Detection Flag OVFmn The length of the transferred data SCI0 7 digit 8 digit or 9 bit Note 1 SCI1 SCI2 7 to 16 bits Transfer rate Max fMCK 6 bps SDRmn 15 9 2 Min fCLK 2 215 128 bps Data phase Normal phase output default high Inverting output default low Parity bits You can choose from the following ...

Page 693: ...ion operation configuration register mn SCRmn baud rate configuration received data register Note2 Note1 Note 1 Limited to SCR01 registers other fixed as 1 2 When communicating with a 9 bit data length bit0 8 of the SDRm1 register is the setting area for sending data Only UART0 can communicate with a data length of 9 bits Note This example is the setting method for SCI0 The data length of SCI1 SCI...

Page 694: ...m Not used in this mode e serial output register m SOm Not used in this mode g serial channel start register m SSm Only set bit of target channel to 1 Note 1 m Unit number m 0 2 2 Fixed setting in UART receive mode Cannot be set initial value is set This is a bit that cannot be used in this mode and the initial value is set if it is not used in other modes 0 1 Set 0 or 1 according to the user s pu...

Page 695: ...via Configure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 make Semn to 1 operation enable state and wait for start bit detection Note that at least 4 fMCK clocks must be spaced after the RXEmn position of the SCRmn register 1 and then the SSmn position 1 Figure 19 105 Abort steps for UART reception termination configuration st...

Page 696: ...figure port register and port mode register set data output of target channel to valid set SSmn bit of target channel to 1 make Semn to 1 operation enable state and wait for start bit detection restart configuration completes clear error flag when FEF PEF OVF flag remains at set state erase via serail flag clear trigger register mn SIRmn modify SPSm register configuration re configure when modifin...

Page 697: ...pin INTSRq shift register mn TSFmn SDRmn SEmn STmn SSmn transmit data1 transmit data 2 data reception 1 data reception 2 data reception 3 shift operation shift operation data reception data reception data reception shift operation transmit data 3 Note m Unit number m 0 2 n Channel number n 1 3 mn 01 03 11 21 r channel number r n 1 q UART number q 0 3 ...

Page 698: ...ount set to enable interrupt after clear interrupt request flag IFxx and release interrupt mask MKxx start receiving via detecting start bit read received data and write into storage region incremental counting of received data count update received data pointer SCI initial configuration transmission completion interrupt normal reception write transmit data to SDRmn 7 0 TXDq register 8 bits or SDR...

Page 699: ...to set the serial data register mn SDRmn to SDRmn 15 9 to 0000000B and 0000001B Note 1 Because when using UART the value of SDRmn 15 9 is the value of bit15 9 of the SDRmn register 0000010B 1111111B so it is 2 to 127 2 m unit number m 0 2 n channel number n 0 3 mn 00 03 10 11 20 21 The operating clock fMCK depends on bit15 of the serial clock selection register m SPSm and the serial mode register ...

Page 700: ... 213 3 91kHz X X X X 1 1 1 0 fCLK 214 1 95kHz X X X X 1 1 1 1 fCLK 215 977Hz 1 0 0 0 0 X X X X fCLK 32MHz 0 0 0 1 X X X X fCLK 2 16MHz 0 0 1 0 X X X X fCLK 22 8MHz 0 0 1 1 X X X X fCLK 23 4MHz 0 1 0 0 X X X X fCLK 24 2MHz 0 1 0 1 X X X X fCLK 25 1MHz 0 1 1 0 X X X X fCLK 26 500kHz 0 1 1 1 X X X X fCLK 27 250kHz 1 0 0 0 X X X X fCLK 28 125kHz 1 0 0 1 X X X X fCLK 29 62 5kHz 1 0 1 0 X X X X fCLK 210...

Page 701: ... Clock fMCK SDRmn 15 9 The calculated value of the baud rate The error from the target baud rate 300bps fCLK 29 103 300 48bps 0 16 600bps fCLK 28 103 600 96bps 0 16 1200bps fCLK 27 103 1201 92bps 0 16 2400bps fCLK 26 103 2403 85bps 0 16 4800bps fCLK 25 103 4807 69bps 0 16 9600bps fCLK 24 103 9615 38bps 0 16 19200bps fCLK 23 103 19230 8bps 0 16 31250bps fCLK 23 63 31250 0bps 0 0 38400bps fCLK 22 10...

Page 702: ...Baud rate calculation k SDRmn 15 9 1 Nfr 1 frame length bits of data start bit data length parity bit stop bit Note m Unit number m 0 2 n Channel number n 1 3 mn 01 03 11 21 Fig 19 109 The allowable range of baud rates at the time of reception in the case of frame length 11 bits of 1 data SCI data frame length min allowed data frame length max allowed data frame length latch timing sequence start ...

Page 703: ...rame error occurs Software operation Hardware status remark Read the serial data register mn SDRmn The BFFmn bit of the SSR mn register is 0 and channel n is in a receivable state This is to prevent overflow errors from occurring at the end of the next receive during mishandling Read the serial status register mn SSRmn The error class is judged and the reading value is used to remove the error fla...

Page 704: ...mpty interrupt continuous transfer mode Error detection flags not The length of the transferred data 8 bits Transfer Rate Note Max fMCK 6 bps SDR00 15 9 2 Min fCLK 2 215 128 bps Data phase Normal phase output default high Inverting output default low Parity bits There are no parity bits Stop bit 1 additional bit Data direction LSB takes precedence Note it must be used within the scope of periphera...

Page 705: ...ster device Therefore if the baud rate error of the slave is not greater than 15 of the communication can be carried out A summary of the send operation of LIN is shown in Figure 19 112 Figure 19 112 The send operation of a LIN wake up signal frame interval field sync field identifier data field checksum data field TxD0 output 8 bit Note1 13 bit Note2 BF transmit 55H transmit data transmit data tr...

Page 706: ...es modify baud rate of BF recover baud rate transmit sync field 55H TxD0 transmit sync field BFF00 0 Data TxD0 Yes No BFF00 0 Yes all data transmit completed TSF00 0 LIN transmit completes Yes Yes No No No wait buffer empty transmit ID checksum data wait buffer empty transmit ID checksum data wait for transmit completion completes the transmission to LIN Bus hardware operation reference generate w...

Page 707: ... is interrupted INTSRE0 Error detection flags Frame Error Detection Flag FEF01 Overflow Error Detection Flag OVF01 The length of the transferred data 8 bits Transfer Rate Note Max fMCK 6 bps SDR01 15 9 2 Min fCLK 2 215 128 bps Data phase Normal phase output default high Inverting output default low Parity bits No parity bits no parity Stop bit 1 additional bit Data direction LSB takes precedence N...

Page 708: ... signal is detected to measure the low level width of BF set TM03 to measure pulse width and then enter the BF receive waiting state 2 If the falling edge of BF is detected the TM03 begins to measure the low level width and snaps on the rising edge of BF Based on the captured value it is a BF signal 3 When the BF reception ends normally TM03 must be set to measure the pulse interval and the interv...

Page 709: ... ends No Yes No No Yes Yes Yes No measure RxD0 Signal low voltage width via TM03 detect BF Wait SBF detection wait BF detection If length 11 bits then consider as BF configure as interval of measurement falling edges ignore 1st INTTM03 measure SF 5th falling edge interval accumulate 4 times capture value modify TM03 to measure low voltage width in order to measure interval field divide accumulated...

Page 710: ... port input RxD0 used for reception to be fed into an external interrupt INTP0 and timer array unit without external wiring Figure 19 116 Port structure diagram for LIN receive operation port mode PMxx Pxx RxD0 output latch Pxx RxD0 input selector selector Pxx INTP0 INTP0 input port input switch control ISC0 selector port mode PMxx Pxx TI03 output latch Pxx selector ISC0 0 set INTP0 pin input sign...

Page 711: ... the wake signal and the start of communication Channel 3 of the universal timer unit detection of baud rate error detection of interval segment BF Purpose Detects the length of the synchronization segment SF and detects baud rate error by dividing its length by the number of bits the interval between the RxD0 input edges is measured by snapping mode Measure the low level width to determine if it ...

Page 712: ...ify the address with a high 7 bits and R W control with the lowest bit Generate start and stop conditions via software Interrupt function End of transfer interrupted Error Detection Flag ACK error Function not supported by Simple I2C Slave sending Slave receiving Multi master function quorum failure detection function Wait for detection feature Note When receiving the last data if you write 0 to t...

Page 713: ...d to end of transmit interrupts buffer null interrupts cannot be selected Error detection flags ACK Error Detection Flag PEFmn The length of the transferred data 8 bits send the high 7 bits as the address and the lower 1 bit as the R W control Transfer rate note 2 Max fMCK 4 Hz SDRmn 15 9 1 fMCK Object Channel s operating clock frequency However it must be at I2 The following conditions are met in...

Page 714: ...ition SOEmn bit is 1 channel n operational clock fMCK 0 SPSm register configured pre scaler output clock CKm0 1 SPSm register configured pre scaler output clock CKm1 Operation mode of channel n 0 Transmit completion interrupt stop bit configuration 01B append 1 bit ACK parity check bit configuration 00B no parity check baud rate configuration configuration of transmit data Address R W Note1 Note1 ...

Page 715: ...se universal serial communication unit from reset state start providing clock configure operational clock configure operational mode etc configure communication format configure transmit baud rate configure operationl clock fMCK scaled transmission clock configure serial data SOmn and serial clock CKOmn initial output voltage set 1 via configure port register port mode register and port output mod...

Page 716: ...cess flow Figure 19 119 Timing diagram of the address segment sent address field transmit bit operation Somn bit operation shift register mn SDAr input SDAr output SDLr output address shift operation Remark m unit number m 0 2 n channel number n 0 3 r IIC number r 00 01 10 11 20 21 30 31 mn 00 03 10 11 20 21 ...

Page 717: ...e address and R W data to SIOr SDRmn 7 0 interrupt occurred for transmit completion Yes No ACK acknowledged Yes communication error handling No confirm slave device Ack acknowledgement via PEFmn bit If it is ACK PEFmn 0 then enter into next process step if is NACK PEFmn 1 then enter into error handling wait for address field transmission completion clear interrupt request flag transmit address fie...

Page 718: ...interrupts cannot be selected Error detection flags ACK Error Flag PEFmn The length of the transferred data 8 bits Transfer rate note2 Max fMCK 4 Hz SDRmn 15 9 1 fMCK The operating clock frequency of the object channel However the following conditions must be met in each mode of I2C Max 1MHz Enhanced Quick Mode Max 400kHz fast mode Max 100kHz standard mode Data level Normal phase output default hi...

Page 719: ...operate this register wihle data is transmitting or receiving f serial channel start register m SSm do not operate this register wihle data is transmitting or receiving baud rate configuration Note4 configuration of transmit data Note1 Note1 Note2 Note3 Note5 Note5 Note5 Note5 Note5 Note5 Note5 Note5 Note 1 Limited to SMR01 SMR03 SMR11 SMR21 registers 2 Limited to SCR00 SCR02 SCR10 SCR20 registers...

Page 720: ...n starts data transmission ends Write data to SIOr SDRmn 7 0 No ACK acknowledged Yes communication error handling No confirm slave device Ack acknowledgement via PEFmn bit If it is ACK PEFmn 0 then enter into next process step if is NACK PEFmn 1 then enter into error handling wait for transmission completes clear interrupt request flag generate stop condition address field transmit completes start...

Page 721: ...annot be selected Error detection flags There are only overflow error detection flags OVFmn The length of the transferred data 8 bits Transfer rate note 2 Max fMCK 4 Hz SDRmn 15 9 1 fMCK The operating clock frequency of the object channel However the following conditions must be met in each mode of I2C Max 1MHz Enhanced Quick Mode Max 400kHz fast mode Max 100kHz standard mode Data level Normal pha...

Page 722: ... transmitting or receiving f serial channel start register m SSm do not operate this register wihle data is transmitting or receiving Note1 Note1 Note2 Note3 baud rate configuration Note4 Note5 Note5 Note5 Note5 Note5 Note5 Note5 Note5 virtual transmit data configuration FFH Note 1 Limited to SMR01 SMR03 SMR11 SMR21 registers 2 Limited to SCR00 SCR02 SCR10 SCR20 registers 3 Limited to SCR00 regist...

Page 723: ...ceiving data b The case of receiving the last data shift register mn SDAr input SDAr output SCLr output virtual data FFH receiving data virtual data FFH receiving data allow serial communication output stop serial commnication output shift operation reception of last byte data IIC stop operating stop condition Somn bit operation Somn bit operation CKOmn bit operation shift operation Remark m unit ...

Page 724: ...last data write 0 to SOEmn bit write virtual data FFH to SIOr SDRmn 7 0 does transmission completion interrupt occur No read SIOr SDRmn 7 0 No data transmission completes No cofigure channel operation mode to receiving restart operation disable outupt in order not to acknowledge the last piece of data start receiving operation read receiving data count and processing store into RAM etc Note that t...

Page 725: ...eration stop condition Note That at the time of reception the serial output enable register m SOEm of the SOEmn position 0 before receiving the last data Fig 19 128 Flowchart of generating a stop condition stop condition generation starts Write 1 to STmn bit SEmn 0 Write 0 to SOEmn bit Write 0 to SOmn bit Write 1 to CKOmn bit wait Write 1 to SOmn bit IIC communication completes operation stop stat...

Page 726: ...ecification the low level width of the SCL signal is greater than the high level width Therefore if set to 400kbps in fast mode or 1Mbps in enhanced fast mode the low level width of the SCL signal output is less than I2C The specification value of the bus SDRmn 15 9 must be set to meet the I2 C bus specifications Note 1 Because the value of SDRmn 15 9 is the value of bit15 9 of the serial data reg...

Page 727: ... fCLK 24 2MHz 0 1 0 1 X X X X fCLK 25 1MHz 0 1 1 0 X X X X fCLK 26 500kHz 0 1 1 1 X X X X fCLK 27 250kHz 1 0 0 0 X X X X fCLK 28 125kHz 1 0 0 1 X X X X fCLK 29 62 5kHz 1 0 1 0 X X X X fCLK 210 31 25kHz 1 0 1 1 X X X X fCLK 211 15 63kHz Other than the above Disable settings NoteWhen you change the clock selected as fCLK change the value of the system clock control register CKC you must stop the ope...

Page 728: ...directly to the SDIRmn register only errors during the read operation can be cleared Read the serial data register mn SDRmn Clear the trigger register mn to the serial flag SDIRmn 写 1 Software operation Hardware status remark Read the serial status register mn SSRmn The error class is judged and the reading value is used to remove the error flag Clears the error flag By writing the read value of t...

Page 729: ...tus and data through the hardware This feature simplifies the I2 C bus control part of the application Because the SCLAn pin and SDAAn pin of the serial interface IICA are used as open drain outputs the serial clock line and serial data bus require pull up resistors In sleep mode when the extension code of the autonomous control device or the address of the local station is received the deep sleep...

Page 730: ...BAT32G1x9 user manual Chapter 20 Serial interface IICA www mcu com cn 730 1149 Rev 1 02 Figure 20 1 diagram of the serial interface IICA ...

Page 731: ...l bus is shown in Figure 20 2 Figure 20 2 example of a serial bus structure for I2C bus SCLAn SDAAn SCLAn SDAAn SCLAn SDAAn SCLAn SDAAn SCLAn SDAAn master control CPU2 slave CPU2 address 1 slave CPU3 address 2 address 3 slave IC address N slave IC master control CPU1 slave CPU1 address 0 serial data bus serial clock Note n 0 1 ...

Page 732: ...ntrol Register PMCxx Port Multiplexing Function Configuration Register PxxCFG Note 1 n 0 1 2 This product can multiplex the IICA input output pin function to multiple ports When a port is configured for multiplexing on the IICA pin the N channel open drain output VDD EVDD withstand voltage mode of the port is designed to automatically open i e the POMxx register does not require user settings List...

Page 733: ...r generating a reset signal the value of this register changes to 00H Figure 20 3 Format of the IICAn shift register n IICAn After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IICAn Note 1 During data transfer data cannot be written to the IICAn registers 2 The IICAn register can only be read and written during the waiting period Access to the IICAn registers in the communication state is prohibited excep...

Page 734: ...th or 9th serial clock set by the WTIMn bit Interrupt request set via SPIEn bit due to detection of a stop condition Note WTIMn bit bit3 of IICA control register n0 IICCTLn0 SPIEn bit bit4 of IICA control register n0 IICCTLn0 20 2 7 Serial clock control circuitry In master mode this circuit generates the output from the sample clock to the clock of the SCLAn pin 20 2 8 Serial clock wait control ci...

Page 735: ... 1 STTn bit bit1 of IICA control register n0 IICCTLn0 SPTn bit bit0 of IICA control register n0 IICCTLn0 IICRSVn bit bit0 of IICA flag register n IICFn IICBSYn bit bit6 of IICA flag register n IICFn STCFn bit bit7 of IICA flag register n IICFn STCENn bit bit1 of IICA flag register n IICFn 2 n 0 1 ...

Page 736: ...owing registers Peripheral enable register 0 PER0 IICA control register n0 IICCTLn0 IICA flag register n IICFn IICA status register n IICSn IICA control register n1 IICCTLn1 IICA low level width setting register n IICWLn IICA high level width setting register n IICWHn Port Mode Register PMxx Port Mode Control Register PMCxx Port Multiplexing Function Configuration Register PxxCFG Note n 0 1 ...

Page 737: ...e IICAnEN bit 1 When the IICAnEN bit is 0 the value of the control register of the serial interface IICAn is the initial value ignoring the write operation port multiplexing function configuration register PxxCFG port mode registers PMxx and port mode control registers PMCxx IICA control register n0 IICCTLn0 IICA flag register n IICFn IICA status register n IICSn IICA control register n1 IICCTLn1 ...

Page 738: ...nditions are met Boot as master device after detecting a stop condition Addresses match or extended codes are received after the start condition is detected Clear condition LRELn 0 1 Set condition LRELn 1 Automatically clears after execution When resetting Set by command WRELn notes 2 3 Pending release 0 Do not dismiss the wait 1 Lift the wait Clears automatically after the wait is lifted If the W...

Page 739: ...ck low and wait for the master During address transmission regardless of the setting of this bit an interrupt is generated on the falling edge of the 9th clock After the address transfer ends the setting for this bit is there Effect The 9th clock descent edge of the master device during address transfer enters a waiting state The slave that receives the local station address is generating a reply ...

Page 740: ...ceive Disables this position 1 during transmission This position 1 can only be placed during the waiting period when ACKEn is at position 0 and notifying the slave that receiving it has completed Master Send During the Ack the start condition may not be generated properly This position 1 must be placed during the wait period after the 9th clock is output Prohibit and Trigger of Stop Condition SPTn...

Page 741: ...sition 1 is placed during the wait after 8 clocks are output it is the 9th after the wait is lifted Stop conditions are generated during high levels of clocks The WTIMn bit must be set from 0 to 1 during the wait period after the output of 8 clocks and during the wait period after the output of the 9th clock SPTn position 1 After placing the SPTn position 1 it is forbidden to place this position 1...

Page 742: ...re 20 6 Format of IICA status register n IICSn 1 3 After reset 00H R symbol 7 6 5 4 3 2 1 0 IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn MSTSn Confirmation flag for the master status 0 Slave state or communication standby 1 Master communication status Clear condition MSTSn 0 1 Set condition MSTSn 1 When a stop condition is detected When the ALDn bit is 1 arbitration failed Cleared because the L...

Page 743: ...ine as high impedance 1 in the sending state Set to output the value of the SOn latch to the SDAAn line valid after the falling edge of the 9th clock byte of the 1st byte Clear condition TRCn 0 1 Position condition TRCn 1 master and slave the master device When a stop condition is detected When the build starts condition Cleared because the LRELn bit is 1 Exit Communication LSB transmit direction ...

Page 744: ...cted indicating that it was in the process of address transfer Clear condition STDn 0 1 Position condition STDn 1 When a stop condition is detected When the 1st clock rises after the next byte of the address is transmitted Cleared because the LRELn bit is 1 Exit Communication When the IICEn bit changes from 1 to 0 stops running When resetting When a start condition is detected SPDn Detection of st...

Page 745: ... operation instruction However only the STTn clear flag STCFn and the I2 C bus status flag IICBSYn can be read The communication appointment function is allowed or disabled by the IICRSVn bit setting and the initial value of the IICBSYn bit is set by the STCENn bit Only bit7 IICEn 0 can only write IICRSVn bits and STCENn bits After allowing operation only the IICFn registers can be read After gene...

Page 746: ...art enable triggering 0 After allowing run IICEn 1 a start condition is allowed to be generated by detecting a stop condition 1 After allowing a run IICEn 1 the start condition is allowed to be generated without detecting the stop condition Clear condition STCENn 0 1 Position condition STCENn 1 Clear by command When a start condition is detected When resetting Set by command IICRSVn The communicat...

Page 747: ...will wupn position 1 When the process After the address matches or the extension code is received the WUPn bit must be cleared to 0 Can participate in subsequent communication by clearing the WUPn bit 0 you need to cancel the wait and write the send data after the WUPn bit is cleared 0 In the state where the WUPn bit is 1 the interrupt timing when the address matches or the extension code is recei...

Page 748: ... Operates in Fast Mode Max Transfer Rate 400kbps or Enhanced Fast Mode Max Transfer Rate 1Mbps DFCn Operational control of digital filters 0 Digital filter OFF 1 Digital filter ON Digital filters must be used in fast mode or enhanced fast mode Digital filters are used to eliminate noise Whether the DFCn position is 1 or the clear 0 the transmission clock is unchanged PRSn Control of the running cl...

Page 749: ... the time set by IICWLn Figure 20 9 The format of the IICA low level width setting register n IICWLn After reset FFH R W Symbol 7 6 5 4 3 2 1 0 IICWLn 20 3 7 IICA high level width setting register n IICWHn This register controls the SCLAn pin signal high level width and SDAAn pin signal of the serial interface IICA output The IICWHn register is set by the 8 bit memory operation instruction Must be...

Page 750: ...t mode register PMx and the port output latch Px must be placed at 0 When the IICEn bit bit7 of the IICA control register n0 IICCTLn0 is 0 P The xx SCLAn pin and the Pxx SDAAn pin are low level outputs fixed so the IICEn must be placed 1 After switching to output mode Set the PM x register via the 8 bit memory operation instruction After the reset signal is generated the value of this register cha...

Page 751: ...the inputs are Schmidt inputs 2 SDAAn Input output multiplexing pins for serial data The outputs of both the master and slave devices are N channel open drain outputs and the inputs are Schmidt inputs Because the outputs of the serial clock line and serial data bus are N channel open drain outputs an external pull up resistor is required Figure 20 11 Pin Structure Diagram master control device clo...

Page 752: ...IICWHn 1 2μs tR tF f MCK Standard mode IICWLn 4 7μsf MCK IICWHn 5 3μs tR tF f MCK Enhanced quick mode IICWLn 0 1 50μsf MCK IICWHn 0 50μs tR tF f MCK Note 1 The maximum operating frequency of the IICA Operating Clock fMCK is 20MHz Max The IICA control register n1 IICCTLn1 must only be placed when the f CLK exceeds 20MHz bit0 PRSn is set to 1 2 In the case of setting the transmission clock the minim...

Page 753: ...ed on the serial data bus of theI2C bus The respective transmission timings for and Stop Condition are shown in the following figure Figure 20 12the 12 I2C bus SCLAn SDAAn start condition address ACK ACK ACK data data stop condition generation starts R W The master generates start conditions slave addresses and stop conditions Both the master and slave devices can generate a reply ACK in general t...

Page 754: ...re the signals generated when the master device starts serially transmitting to the slave When used as a slave the start condition is detected Figure 20 13 starting conditions SCLAn SDAAn In the state where a stop condition SPDn bit0 1 of IICA status register n IICSn is detected if the IICA is detected Bit1 STTn of the control register n0 IICCTLn0 is set to 1 to start the output condition If a sta...

Page 755: ...IICAn Note If data other than the local station address or extension code is received while the slave is running INTIICAn is not generated If the 8 bit data consisting 20 5 3The designation of the transmission directionof the Transmission Direction in 20 5 3 is written to the IICA shift register n IICAn the output address The received address is written to the IICAn register The slave address is a...

Page 756: ...hat automatically generates a response Sets bit3 TRCn of the IICSn register by the 8th bit of data that follows from the 7 bit address information In the case of receiving TRCn 0 1 it is usually necessary to place the ACKEn position 1 During the slave receive run TRCn 0 1 cannot receive data or does not need the next data the ACKEn must be cleared to 0 to inform the master that the data cannot be ...

Page 757: ...s the signal generated when the master ends serial transmission to the slave When used as a slave a stop condition is detected Figure 20 17 Stop condition SCLAn SDAAn If the bit0 SPTn of the IICA control register n0 IICCTLn0 is set to 1 a stop condition is generated If a stop condition is detected set bit0 SPDn of the IICA status register n IICSn to 1 and generates INTIICAn when bit4 SPIEn of the ...

Page 758: ... states are lifted the next transfer can begin Figure 20 18 Wait 1 2 1 The master device waits for 9 clocks and the slave device waits for 8 clocks Master Transmit Slave Receive ACKEn 1 enter into wait state after output 9th Clock write data into IICAn release from wait master device resume Hi Z state slave device stays in wait state low voltage slave device waits master device waits H IICAn SCLAn...

Page 759: ...n SDAAn transmis sion line slave device master device generates according to pre configured ACKEn Note ACKEn Bit2 of IICA control register n0 IICCTLn0 WRELn Bit5 of the IICA control register n0 IICCTLn0 A wait state is automatically generated by bit3 WTIMn by setting the IICA control register n0 IICCTLn0 Typically on the receiver side if the bit5 WRELn of the IICCTLn0 register is 1 or give the IIC...

Page 760: ...r must be placed at 1 To generate a restart condition after a wait is lifted the bit1 STTn of the IICCTLn0 register must be placed at 1 To generate a stop condition after lifting the wait the bit0 SPTn of the IICCTLn0 register must be set to 1 Only one release process can be performed for a wait For example if you write data to the IICAn register after de waiting by placing the WRELn position 1 th...

Page 761: ...generates INTIICAn on the descending edge of the 8th clock If the addresses are different after restarting INTIICAn is generated on the falling edge of the 9th clock but does not enter the waiting state 2 If the contents of the received address and the slave address register n SVAn are different and the extension code is not received THE INTIICAn is not generated and does not enter the waiting sta...

Page 762: ...nerated limited to the case of SPIEn 1 20 5 9 The detection method for address matching In I2C bus mode the master device can select a specific slave by sending a slave address Address matching can be automatically detected by hardware When the slave address sent by the master device and the set address of the slave address register n SVAn are the same or only the extension code is received an IND...

Page 763: ... IICSn COIn Bit4 of IICA status register n IICSn 3 The processing after an interrupt request occurs depending on the subsequent data of the extension code and is processed by software If an extension code is received while the slave is running it is participating in the communication even if the addresses are different For example if you do not want to run as a slave after receiving an extension c...

Page 764: ...flag ALDn of the IICA status register n IICSn to 1 and places the SCLAn Both the line and the SDAAn line are placed in a high impedance state releasing the bus In the event of the next interrupt request e g a stop condition is detected at the 8th or 9th clock the ALDn bit is 1 via software to detect the failure of the quorum For the timing of interrupt requests please refer to Generation Timing an...

Page 765: ... stop condition SPIEn 1 You want to generate a restart condition but the data is low The descending edge of the 8th or 9th clock after the byte transfer is note 1 You want to build a restart condition but a stop condition is detected Note 2 when generating a stop condition SPIEn 1 You want to generate a stop condition but the data is low The descending edge of the 8th or 9th clock after the byte t...

Page 766: ...a arbitration failure it enters wake up standby at the same time as the address is sent To use the wake function in deep sleep mode you must place the WUPn at 1 The address can be received independent of the operating clock Even in this case an interrupt request signal INTIICAn is generated when the local station address and extension code are received After this interrupt is generated the WUPn bi...

Page 767: ...to the interrupt request INTIICAn generated by the serial interface IICA the deep sleep mode must be removed through the following procedure The next IIC communication is the case of the operation of the master control device Figure 20 22 22 The next IIC communication is the case for the slave to run The situation of returning via ANTIICAn interrupt The same process as Figure 20 21 Cases returned ...

Page 768: ... master device START SPIEn 1 WUPn 1 wait deep sleep instruction release deep sleep mode WUPn 0 INTIICAn 1 No Wait Read IICSn after confirming serial interface IICA operation status process accordingly deep sleep mode state release deep sleep mode using other interrupt than INTIICAn generate stop condition or selected as slave device wait for 5 fMCK clocks Note n 0 1 ...

Page 769: ... 1 after the release of the bus stop condition detected is detected by the generated interrupt request signal INTIICAn if given IICA shifts the register n IICAn to write the address and automatically begins to communicate as the master device The data written to the IICAn register is invalid until a stop condition is detected When stTn is positioned 1 it is decided whether to run as a start condit...

Page 770: ...er n STTn Bit1 of IICA control register n0 IICCTLn0 STDn Bit1 of the IICA status register n IICSn SPDn Bit0 of IICA status register n IICSn Accept communicationFigure 20 24 After bit1 STDn of the IICA status register n IICSn becomes 1 and before a stop condition is detected it will be Bit1 STTn of the IICA control register n0 IICCTLn0 is placed 1 Make a communication appointment Figure 20 24 Recep...

Page 771: ...nning Remarks 1 STTn Bit1 of IICA control register n0 IICCTLn0 MSTSn Bit7 of the IICA status register n IICSn IICAn IICA shift register n IICWLn IICA low level width setting register n IICWHn IICA high level width setting register n tF The descent time of the SDAAn signal and the SCLAn signal fMC IICA operating clock frequency 2 n 0 1 2 Case where the communication appointment function is prohibit...

Page 772: ... When the SDAAn pin is low and the SCLAn pin is high I2C macros are considered SDAAn citations if I2C is allowed to run and participate in communication in the middle the foot changes from high to low start condition detected If the value on the bus is recognized as an extension code at this point a reply is returned that interferes with I2C communication with other devices To avoid this I2C must ...

Page 773: ... participates in communication as a release state This process is roughly divided into initial setup communication waiting and communication processing The processing designated as a slave due to the failure of the arbitration is omitted here and only the processing used as the master device is omitted Join the bus after performing the Initial Setup section at startup and then wait for a communica...

Page 774: ... generate stop condition wait for detection of stop condition Yes Yes STTn 1 prepare starting communication generate start condition Write IICAn start communicating determined address and transmission direction does INTIICAn interrupt occur No Yes ACKDn 1 Yes TRCn 1 Yes Write IICAn does INTIICAn interrupt occur No Yes ACKDn 1 Yes transmission completes Yes restart Yes No No SPTn 1 END ACKEn 1 WTIM...

Page 775: ...er masters to appoint slave device Wait for communication start request determined by user program start master operation Yes with communication start request SPIEn 1 IICRSVn 0 SPIEn 0 does INTIICAn interrupt occur Yes No No communication start request Yes A B No slave operation No Waiting for a communication request 1 release serial interface IICA from reset state start providing clock configure ...

Page 776: ...eservation function then enter into wait state wait time as following IICWLn configured value IICWHn configured value 4 fMCK tF 2 Note communication process B IICBSYn 0 Yes STTn 1 Wait D STCFn 0 Yes ensure wait time via software Note prepare starting communication generate stop condition wait for 5 fMCK clocks No No does INTIICAn interrupt occur EXCn 1 or COIn 1 Yes slave operation No wait to rele...

Page 777: ... No MSTSn 1 2 No Yes Read IICAn transmission completes start receiving Yes Yes ACKEn 0 WTIMn 1 WRELn 1 does INTIICAn interrupt occur No MSTSn 1 2 No Yes Yes wait for detecing acknowledgement No 2 EXCn 1 or COIn 1 slave operation Yes 1 No does not participant communication communication process No Remarks 1 The format of transmission and reception must conform to the specifications of the product i...

Page 778: ...ady sign This flag indicates that data communication can take place In the usual data communication as with the INTIICAn interrupt the interrupt processing department is placed and cleared by the main processing department When communication begins the flag is cleared by interrupt handling However when sending the first data interrupt processing does not set the ready flag in place so the first da...

Page 779: ...gured to be input mode and output latch set to 0 select transmission clock configure local address configure start condition allows I2C bus outupt after configure Port from input mode to output mode initial configuration interrupt handling Yes Write IICAn communcation mode flag 1 Yes communication direction flag 1 Yes ready flag 1 clear ready flag Yes ACKDn 1 No clear communication mode flag WRELn...

Page 780: ... the communication ends If the addresses are the same set to communication mode and dismiss the wait then return from interrupt clear the ready flag When sending and receiving data the I2C bus remains waiting and returns from the interrupt as soon as the ready flag is set Note that 1 3 above corresponds to 1 3 of Figure 20 29 Slave run step 2 2 Figure 20 29 Slave run step 2 generate INTIICAn SPDn ...

Page 781: ...IICAn The values of the data send and receive timing the timing of the generation of the INTIICAn interrupt request signal and the IICA status register n IICSn when the INTIICAn signal is generated are shown below Remarks 1 ST Start condition AD6 AD0 Address R W The specified transmission direction ACK Acknolwdge D7 D0 Data SP Stop Condition 2 n 0 1 ...

Page 782: ... IICSn 1000XX00B set SPTn bit to 1 5 IICSn 00000001B Note to generate stop condition must set WTIMn bit to 1 and modify INTIICAn interrupt requet signal generation timing sequence Remark must generate only generate while SPIEn bit is 1 any X SPTn 1 ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000X100B 3 IICSn 1000XX00B set SPTn bit to 1 4 I...

Page 783: ...riginal configuration must set WTIMn bit to 0 3 to generate stop condition must set WITIMn bit to 1 and modify INTIICAn interrupt request signal generation timing sequence Remark must generate only generate while SPIEn bit is 1 Any X SPTn 1 ST AD6 AD0 R W ACK D7 D0 ACK 4 5 STTn 1 3 2 IICSn 1000X000B set WTIMn bit to Note1 4 IICSn 1000X110B 5 IICSn 1000X000B set WTIMn bit to Note3 ii In the case of...

Page 784: ...XX00B set SPTn bit to 1 5 IICSn 00000001B Note to generate stop condition must set WITIMn bit to 1 and modify INTIICAn interrupt request signal generation timing sequence SPTn 1 Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 1010X110B 2 IICSn 1010X100B 3 IICSn 1010XX00B set SPTn bit to 1 4 IICSn 0000...

Page 785: ...ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X100B 3 IICSn 0001XX00B 4 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X Note n...

Page 786: ... IICSn 0001X000B 4 IICSn 0001X000B 5 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0001X110B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 same SVAn after restart ST AD6 AD0 R W ACK D7 D0 ACK SP 1 4 5 1 IICSn 0001X110B 2 IICSn 0001XX00B 4 IICSn 0001XX00B 5 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0001X110B Remark must generate only ...

Page 787: ...00B 4 IICSn 0010X000B 5 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010X010B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 address is different after restart extension code ST AD6 AD0 R W ACK D7 D0 ACK SP 1 5 6 1 IICSn 0001X110B 2 IICSn 0001XX00B 5 IICSn 0010XX00B 6 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010X010B 4 4 IICSn 001...

Page 788: ...1 IICSn 0001X110B 2 IICSn 0001X000B 4 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 00000110B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 different addresses after restart non extension code ST AD6 AD0 R W ACK D7 D0 ACK SP 1 4 1 IICSn 0001X110B 2 IICSn 0001XX00B 4 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 00000110B Remark must gene...

Page 789: ...n the case of WTIMn 0 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 4 IICSn 0010XX00B 5 IICSn 00000001B 2 3 IICSn 0010X100B Remark must generate onl...

Page 790: ...00B 5 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0001X110B 4 4 IICSn 0001X000B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 same SVAn after restart ST AD6 AD0 R W ACK D7 D0 ACK SP 1 5 6 1 IICSn 0010X010B 2 IICSn 0010X110B 5 IICSn 0001XX00B 6 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010XX00B 4 4 IICSn 0001X110B Remark must gener...

Page 791: ...00001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010X010B 4 4 IICSn 0010X000B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 receiving the extension code after restarting ST AD6 AD0 R W ACK D7 D0 ACK SP 1 6 7 1 IICSn 0010X010B 2 IICSn 0010X110B 6 IICSn 0010XX00B 7 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010XX00B 5 IICSn 0010X110B 5 4 4 IICSn ...

Page 792: ...X010B 2 IICSn 0010X000B 4 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 00000X10B Remark must generate only generate while SPIEn bit is 1 any X ii The case of WTIMn 1 different addresses after restart non extension code ST AD6 AD0 R W ACK D7 D0 ACK SP 1 5 1 IICSn 0010X010B 2 IICSn 0010X110B 5 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 3 2 3 IICSn 0010XX00B 4 4 IICSn 00000X10B Remark m...

Page 793: ...unning as a slave after the arbitration fails When used as a master device in a multi master system the MSTSn bit must be read each time an INTIICAn interrupt request signal is generated to confirm the arbitration result a A condition in which arbitration fails during the sending of slave address data i In the case of WTIMn 0 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 0101X110B 2 ...

Page 794: ... 3 IICSn 0001XX00B 4 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X b A condition in which arbitration fails during the sending of an extension code i In the case of WTIMn 0 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 0110X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X Note n 0 ...

Page 795: ... The operation of the arbitration failure not participating in the communication after the arbitration failed When used as a master device in a multi master system the MSTSn bit must be read each time an INTIICAn interrupt request signal is generated to confirm the arbitration result a The case where the arbitration fails during the sending of slave address data WTIMn 1 ST AD6 AD0 R W ACK D7 D0 AC...

Page 796: ...ACK SP 1 2 1 IICSn 01000110B 2 IICSn 00000001B set LRELn bit to 1 via software Remark must generate only generate while SPIEn bit is 1 c A condition in which the arbitration fails while transferring data i In the case of WTIMn 0 1 ST AD6 AD0 R W ACK D7 D0 ACK D7 D0 ACK SP 1 2 3 1 IICSn 10001110B 2 IICSn 01000000B 3 IICSn 00000001B Remark must generate only generate while SPIEn bit is 1 any X Note ...

Page 797: ...CSn 00000001B Remark must generate only generate while SPIEn bit is 1 d A situation where arbitration fails due to restart conditions when transferring data i Non extended codes for example SVAns are different ST AD6 AD0 R W ACK D7 D0 ACK SP 1 3 1 IICSn 1000X110B 2 IICSn 01000110B 3 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 2 Remark must generate only generate while SPIEn bit is 1 any X Note n ...

Page 798: ... 3 IICSn 00000001B ST AD6 AD0 R W ACK D7 D0 ACK 2 set LRELn bit to 1 via software m 0 6 Remark must generate only generate while SPIEn bit is 1 any X e A situation in which arbitration fails due to a stop condition when transferring data ST AD6 AD0 R W ACK D7 Dm SP 1 2 1 IICSn 10000110B 2 IICSn 01000001B m 0 6 Remark must generate only generate while SPIEn bit is 1 Note n 0 1 ...

Page 799: ...CSn 1000X110B 2 IICSn 1000X000B set WTIMn bit to 4 IICSn 01000000B 5 IICSn 00000001B D7 D0 ACK D7 D0 ACK 3 STTn 1 2 3 IICSn 1000X100B set WTIMn bit to 0 Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK SP 1 3 4 1 IICSn 1000X110B 2 IICSn 1000X100B set STTn bit to 1 3 IICSn 01000100B 4 IICSn 00000001B D7 D0 ACK D7 D0 ACK 2 STTn 1 Re...

Page 800: ... 1 ST AD6 AD0 R W ACK D7 D0 ACK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000X000B set WTIMn bit to 3 IICSn 1000XX00B set STTn bit to 1 4 IICSn 01000001B STTn 1 Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK SP 1 2 3 1 IICSn 1000X110B 2 IICSn 1000XX00B set STTn bit to 1 3 IICSn 01000001B STTn 1 Remark must generate only generate whi...

Page 801: ...Sn 1000X110B 2 IICSn 1000X000B set WTIMn bit to 4 IICSn 01000100B 5 IICSn 00000001B D7 D0 ACK D7 D0 ACK 3 SPTn 1 2 3 IICSn 1000X100B set WTIMn bit to 0 Remark must generate only generate while SPIEn bit is 1 any X ii In the case of WTIMn 1 ST AD6 AD0 R W ACK D7 D0 ACK SP 1 3 4 1 IICSn 1000X110B 2 IICSn 1000X100B set SPTn bit to 1 3 IICSn 01000100B 4 IICSn 00000001B D7 D0 ACK D7 D0 ACK 2 SPTn 1 Rem...

Page 802: ...ster n IICSn that indicates the direction of data transmission after the slave address Begin serial communication with the slave The timing diagram of data communication is shown in FIG 20 30and FIG 20 31 The shift of the IICA shift register n IICAn is carried out synchronously with the falling edge of the serial clock SCLAn and the transmit data is transmitted to the SO latch in MSB Prioritize ou...

Page 803: ...k line SDAAn bus data line slave IICAn ACKDn ACK detection STDn ST detection SPDn SP detection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdation state WRELn release from wait TRCn transmit reception H H L L 注2 start condition D17 Note3 Note1 slave device waits master device and slave device wait ACK AD4 AD3 AD2 AD1 Note 1 To remove the wait during the master send the IICAn m...

Page 804: ...9th clock ACKDn 1 The master generates an interrupt on the falling edge of the 9th clock INTIICAn address send end interrupt Slaves with the same address enter a waiting state SCLAn 0 1 and an interrupt INTIICAn address matching interrupt note The master writes and transmits data to the IICAn registers relieving the master of waiting If the slave lifts the wait WRELn 1 the master begins to transmi...

Page 805: ...RCn transmit reception bus SCLAn bus Clock line SDAAn bus data line slave IICAn ACKDn ACK detection STDn ST detection SPDn SP detection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdati on state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L L D27 note 1 slave device waits master device and slave device wait H L note 1 H W D17 D16 D15 D14 ACK D13 D12 ...

Page 806: ...to the master control through hardware The master detects ACK on the rising edge of the 9th clock ACKDn 1 8 Both the master and the slave enter a waiting state SCLAn 0 1 on the falling edge of the 9th clock and both produce interrupts INTIICAn Transmit End Interrupt 9 The master controller writes and sends data to the IICAn register to remove the waiting of the main controller 10 If the slave read...

Page 807: ...n ST detection SPDn SP detection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdat ion state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L L note1 slave device waits master device and slave device wait L D166 D165 D164 ACK D163 D162 D161 D160 note3 ACK D150 note 2 stop condition master device waits D167 Note 1 To remove the wait during the master send...

Page 808: ...ugh the hardware The master detects ACK on the rising edge of the 9th clock ACKDn 1 Both the master and slave enter a waiting state SCLAn 0 1 on the falling edge of the 9th clock and both produce an interrupt INTIICAn end of transmit interrupt The slave reads the received data and dismisses the wait WRELn 1 If the master sets the stop condition trigger set SPTn 1 the bus data line SDAAn 0 1 is cle...

Page 809: ...ine slave IICAn ACKDn ACKdetectio n STDn STdetection SPDn SPdetection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdat ion state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L L slave device waits master device and slave device waits L note2 master device waits H L H D12 D11 D10 D13 AD6 AD5 AD4 AD3 AD2 AD1 slave address restart start condition note1 A...

Page 810: ...ng state SCLAn 0 1 on the falling edge of the 9th clock and both produce interrupts INTIICAn Transmit End Interrupt 1 the slave reads and receives the data and the wait is lifted WRELn 1 2 if the master triggers the start condition again STTn 1 the bus clock line rises SCLAn 1 and the bus data line drops SDAAn 0 1 after the preparation time for the new start condition generate start conditions cha...

Page 811: ...interrupt TRCn transmit reception bus SCLAn bus Clock line SDAAn bus data line slave IICAn ACKDn ACKdetection STDn STdetection SPDn SPdetection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdat ion state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L note2 start condition D17 slave device waits master device and slave device waits ACK note1 R L master ...

Page 812: ...r detects ACK on the rising edge of the 9th clock ACKDn 1 The master generates an interrupt on the falling edge of the 9th clock INTIICAn address send end interrupt Slaves with the same address enter a waiting state SCLAn 0 1 and an interrupt INTIICAn address matching interrupt note The master changes the wait sequence to the 8th clock WTIMn 0 1 The slave writes and sends data to the IICAn registe...

Page 813: ...n transmit reception bus SCLAn bus Clock line SDAAn bus data line slave IICAn ACKDn ACKdetection STDn STdetection SPDn SPdetection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdat ion state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L H slave device waits master device and slave device waits H L L D17 D16 D15 D14 D13 D12 D11 D10 L ACK D27 note1 ACK ...

Page 814: ...End of Transmission Interrupt Because the ACKEn bit of the master is 1 the ACK is sent to the slave through the hardware 9 The master controller reads the received data and cancels the wait WRELn 1 10 The slave detects ACK ACKDn 1 on the rising edge of the 9th clock 11 The slave enters a waiting state on the descending edge of the 9th clock SCLAn 0 1 and produces an interrupt INTIICAn end of trans...

Page 815: ...dat ion state STTn ST trigger SPTn SP trigger WRELn release from wait INTIICAn interrupt TRCn transmit reception bus SCLAn bus Clock line SDAAn bus data line slave IICAn ACKDn ACKdetection STDn STdetection SPDn SPdetection WTIMn 8 or 9 clock cycles waiting ACKEn ACK control MSTSn communicdat ion state WRELn release from wait INTIICAn interrupt TRCn transmit reception H H L slave device waits maste...

Page 816: ...t register n IICAn the slave s wait is lifted and the transfer of data from the slave to the master begins The master generates an interrupt INTIICAn transmit end interrupt on the falling edge of the 8th clock and enters a waiting state SCLAn 0 1 Because ACK control ACKEn 1 occurs the bus data line at this stage becomes low SDAAn 0 1 The master sets the NACK Acknolwdge ACKEn 0 1 and changes the wa...

Page 817: ... is a mode used when serial transfer is not in progress and reduces power consumption 2 3 wire serial I O mode This mode transmits 8 bit or 16 bit data to multiple devices via three lines of serial clock SCK n and serial data bus MISO n and MOSI n Note n 0 1 21 2 Structure of the serial interface SPI Figure 21 1 diagram of the serial interface SPI 移位寄存器发送缓冲寄存器接收缓冲寄存器 MOSI MISO 内部总线 SCK NSS fCLK ...

Page 818: ...terface SPI The serial interface SPI is controlled by the following registers Peripheral enable register 2 PER2 Serial operating mode register SPIMn Serial clock selection register n Transmit buffer register SDROn Receive Buffer Register SDRIn Port Mode Register PMxx Port Mode Control Register PMCxx Port register Pxx Note n 0 1 ...

Page 819: ... PER2 PER2 registers are registers that are set to allow or disable clocking to each peripheral hardware Reduce power consumption and noise by stopping clocking hardware that is not in use To use the SPI function SPInEN must be set to 1 For details see 4 3 8 Perimeter Allow Registers 0 1 2 3 PER0 PER1 PER2 PER3 Note n 0 1 ...

Page 820: ...ceive mode control 0 Receive mode 1 Send Receive mode NSSEnNote4 NSS pin uses selection 0 The NSS pin is not used 1 Use the NSS pin DIRn Data transfer order selection 0 Perform MSB first input output 1 Perform LSB first input output INTMDn Interrupt source selection 0 The end of transfer is interrupted 1 The send buffer is empty interrupt DLSn The setting of the data length 0 8 bits of data length...

Page 821: ...W symbol 7 6 5 4 3 2 1 0 SPICn 0 0 0 CPOLn CPHAn CKS2n CKS1n CKS0n data transmit Specify the receiving timing output timing sequence input timing sequence output timing sequence input timing sequence output timing sequence input timing sequence output timing sequence input timing sequence Note 1 Write TOPICn is prohibited when SPIE n 1 operation enabled 2 The phase type of the data clock after res...

Page 822: ...1 4 status register SPISn Address SPI0 0x40046C10 SPI1 0x40047010 After reset 00H R symbol 7 6 5 4 3 2 1 0 LISTn SDRIFn SPTFn SDRIFn Receive buffer non null flag bits 0 There is no new valid data in the receive cache 1 There is valid data received in the receive cache When the register SDRI is read the bit is cleared to 0 SPTFnNote1 Communication status flag bits 0 Communication interrupt 1 Commun...

Page 823: ...0H Figure 21 5 Format of the transmit buffer register SDROn Address SPI0 0x40046C08 SPI1 0x40047008 After Reset 0000H R W symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROSS n ROSS n 21 3 6 Receive buffer register SDRIn This register stores the received data If bit 6 TRMDn of the serial operating mode register SPIMn is set to 0 the reception begins by reading data from the SDRI During reception data...

Page 824: ...1 Port Mode Register PMxx When using the multiplex port of the SPI pin as the output of S CK SO MO the position of the port mode register PMxx PMCxx corresponding to each port must be 0 When using the multiplexing port of the SPI pin as an input to SCK SI MI the bits 1 P MCxx of the port mode register PMxx corresponding to each port must be used Position 0 At this point the bit of the port registe...

Page 825: ...ter communication begins bit 0 SPTF n of SPISn is set to 1 When the communication of data is complete set the communication completion interrupt request flag SPIIFn and clear SPTFn to 0 Then enable the next communication Precautions 1 When SPTFn 1 during serial communication access to control registers and data registers is prohibited 2 Must be used within the range that satisfies the SCLK Cycle T...

Page 826: ... send receive starts 1 Procedure Figure 21 7 Initial setup steps for master send receive Note n 0 1 The start of the initial setting i Set the PER1 register Set the SPICn register Set the SPIMn register Set the port The end of the initial setting i Removes the reset state of the Universal Serial Unit and begins clock provision Sets the serial clock Set the operating mode Sets the port mode registe...

Page 827: ...ceive Note n 0 1 Start of abort setting i End i of the abort setting SPTFn 0 No Yes Write the SPIMn register Set the PER1 register If there is data being transferred wait for the transfer to end Place the SPIEn at the position 0 and stop the operation of SPIn To use deep sleep mode stop the clock of the SPI unit and set the reset state ...

Page 828: ...SPTF INTSPI 移位运行移位运行 SDRI 接收数据1 接收数据2 shift operation transmit data1 shift operation transmit data2 receiving data1 receiving data2 shift register Write SDRO Fig 21 10 transmit receive timing continuous transmit mode INTMD 1 CPHA 1 CPOL 1 SCK 写SDRO SDRO 发送数据1 SPIE 移位寄存器发送数据2 SPTF INTSPI 移位运行移位运行 SDRI 接收数据1 接收数据2 SDRIF shift register Write SDRO shift operation transmit data1 transmit data2 shift...

Page 829: ...reception begins 1 Procedure Figure 21 11 Initial setup steps for master reception Note n 0 1 The start of the initial setting i Set the PER2 register Set the SPICn register Set the SPIMn register Set the port The end of the initial setting i Removes the reset state of the Universal Serial Unit and begins clock provision Sets the serial clock Set the operating mode Sets the port mode register Ends...

Page 830: ...se deep sleep mode stop the clock of the SPI unit and set the reset state Note 1 Write the SPIMn register Note 1 In receive only mode the SPI transmission is triggered by reading the value of the SDRIn register If the SPI is not aborted in time there may be a redundant transmission after the last read of SDRIn If you want to avoid the last redundant transmission you can turn off SPIE N after waiti...

Page 831: ...49 Rev 1 02 2 Processing process Fig 21 13 Timing diagram of the receiving timing CPHA 1 CPOL 1 SCK 读SDRI SDRI SPIE 移位寄存器接收数据1 SPTF INTSPI 接收移位运行接收移位运行接收数据2 SDRIF shift register Read SDRI Receiving shift operation Receiving shift operation receiving data1 receiving data2 ...

Page 832: ...wait for the clock of the master device to start sending receiving 1 Procedure Figure 21 14 Initial setup steps for slave send receive Note n 0 1 The start of the initial setting i Set the PER1 register Set the SPICn register Set the SPIMn register Set the port The end of the initial setting i Removes the reset state of the Universal Serial Unit and begins clock provision Sets the serial clock Set...

Page 833: ... Note n 0 1 Start of abort setting i End i of the abort setting SPTFn 0 No Yes Write the SPIMn register Set the PER2 register If there is data being transferred wait for the transfer to end Place the SPIEn at the position 0 to stop the operation of the SPI To use deep sleep mode stop the clock of the SPI unit and set the reset state ...

Page 834: ...TF INTSPI 移位运行移位运行 SDRI 接收数据1 接收数据2 transmit data1 transmit data2 receiving data1 receiving data2 shift operation shift operation shift register Fig 21 17 Timing diagram of transmit receive timing continuous transmission mode INTMD 1 CPHA 1 CPOL 1 SCK SDRO 发送数据1 SPIE 移位寄存器发送数据2 SPTF INTSPI 移位运行移位运行 SDRI 接收数据1 接收数据2 SDRIF transmit data1 transmit data2 shift operation shift operation shift regist...

Page 835: ...In wait for the clock of the master device to start receiving 1 Procedure Figure 21 18 Initial setup steps for slave reception Note n 0 1 The start of the initial setting i Set the PER2 register Set the SPICn register Set the SPIMn register Set the port The end of the initial setting i Removes the reset state of the Universal Serial Unit and begins clock provision Sets the serial clock Set the ope...

Page 836: ...eep sleep mode stop the clock of the SPI unit and set the reset state The penultimate m 1 reads out the data Note 1 Write the SPIMn register Note 1 In receive only mode the SPI transmission is triggered by reading the value of the SDRIn register If the SPI is not aborted in time there may be a redundant transmission after the last read of SDRIn If you want to avoid the last redundant transmission ...

Page 837: ...1149 Rev 1 02 2 Processing process Figure 21 20 diagram of the receiving timing CPHA 1 CPOL 1 SCK 读SDRI SDRI SPIE 移位寄存器接收数据1 SPTF INTSPI 接收移位运行接收移位运行接收数据2 SDRIF Receiving shift operation Receiving shift operation receiving data1 receiving data2 shift register Read SDRI ...

Page 838: ...ork capability and complies with the CAN protocol of the ISO 11898 standard 22 1 1 features Complies with ISO 11898 and is tested according to ISO DIS 16845 CAN compliance Standard and extended frames are used for receiving and sending Communication speed Maximum 1Mbps CAN input clock greater than or equal to 8MHz 1 channel has 16 message caches Receive Send History List function Automatic block t...

Page 839: ...h cache can be associated with a send complete interrupt Packet buffers 0 through 7 are designated as transmit packet buffers and can be used for automatic block transfers The message transmission interval is programmable Automatic Block Transfer Function hereinafter referred to as ABT Transfer history list function Remote frame processing Remote frame processing is cached through the transmission...

Page 840: ...rotocol layer and CANRAM in the CAN module 3 CAN protocol layer This function block involves the operation of the CAN protocol and its associated settings 4 CAN RAM This is the CAN memory function block which is used to store message ID message data etc Figure 22 1 diagram of 1 CAN module n BAT32G139 n 0 1 BAT32G179 n 0 1 2 CAN Protocol layer Storage control module Mcm interface CAN receive Intern...

Page 841: ...yers 高 low 1 CAN controller specification 22 2 1 Frame format 1 Standard frame format The standard frame format uses 11 bit identifiers which means it can handle 2048 signals 2 Extend the format frame Extended format frames use 29 bit 11 bit 18 bit identifiers which can handle 2048x218 signals Sets the extended format frame when the implicit level is set for the SRR and IDE bits in the arbitration...

Page 842: ...s you set a delay to wait for the next data frame or remote frame 3 Bus value Bus values are divided into explicit and implicit The dominant value is logically 0 The implicit value is logical 1 When a bus is both dominant and implicit the state of the bus is displayed as dominant 22 2 3 Data frames and remote frames 4 Data frames A data frame consists of 7 different bit fields Figure 22 3 Data fra...

Page 843: ...rt SOF The frame start field is at the beginning of a data frame or remote frame Figure 22 5 Frame Start SOF Note D Dominant 0 R Recessive 1 If a dominant bit is detected in the bus idle state a hard synchronization is performed the current TQ is designated as the SYNC segment If a dominant bit is sampled at a sample point after such a hard synchronization the bit is assigned as SOF If a recessive...

Page 844: ...MSB first Note D Dominant 0 R Recessive 1 Figure 22 7 Arbitration field in extended frame mode arbitration fields control fields identifier 11 bit identifier 1 bit 1bit 18 bit 1 bit Note 1 ID18 through ID28 are identifiers 2 The identifier is sent first for THE MSB Note D Dominant 0 R Recessive 1 Table22 3 RTR Frame configuration The frame type RTR bits Data frames 0 D Remote frames 1 R Table 22 4...

Page 845: ...ecessive 1 In standard format frames the IDE bit of the control field is the same as the r1 bit Table22 5 Data Length Configuration Data length code Data byte calculation DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other values 8 bytes regardless of the value of DLC0 to DLC3 Note ...

Page 846: ...C field Data fields or control fields CRC fields ACK fields CRC delimiter CRC Sequence 15 bit 1 bit Note D Dominant 0 R Recessive 1 The polynomial P X used to generate a 15 bit CRC sequence is represented as follows P X X 15 X 14 X 10 X 8 X 7 X 4 X 3 1 Send Node Sends a sequence of CRC calculations for data from the start frame arbitration field control field and data farm before bit population Re...

Page 847: ... of a data frame or a remote frame Figure 22 12 End of Frame EOF ACK fields Frame interval or overflow frame Frame end 7 bit Note D Dominant 0 R Recessive 1 8 inter frame space Inter frame space is used to distinguish between two frames by inserting between data frames remote frames error frames or overload frames The bus state differs based on the state of the error a Active error node The interf...

Page 848: ...bits Note 1 Bus idle The bus is not in use by any nodes Pending Transfer In a passive error condition 8 hidden bits are sent on the node 2 D Dominant 0 R Recessive 1 In general the gap field is 3 bits if the sending node detects an explicit bit in the third bit of the gap field the send operation will be performed anyway Error status operation Table22 6 Operation in Error state Error status operat...

Page 849: ...output of 6 recessive bits When one node is outputting a passive error flag and another node outputs an explicit bit the passive error flag is not cleared until six consecutive bits of the same polarity are detected 2 Error flag 2 0 6 The node accepts error flag 1 detection bit fill error and then issues this error flag 3 Error delimiter 8 Continuous output of 8 recessive bits If an dominant bit i...

Page 850: ...es 6 bits 8 bits 1 to 6 bits Frame interval or overflow frame overflow flag error identifer overflow flag frame overflow frame Note D Dominant 0 R Recessive 1 Table22 8 Overload Frame field Definition No name Number of digits definition 1 Overload flag 6 Continuous output of 6 dominant bits 2 Overload flags for other nodes 0 to 6 An overload flag is received in the inter frame space and an overloa...

Page 851: ...rough ID28 are the same the standard format remote frame has priority 22 3 2 Bit padding Bit padding is when the level of the same polarity lasts 5 bits and then a bit with opposite polarity is inserted to establish synchronization to prevent bursting errors Table22 10 Bit stuffing Send When sending a data frame or a remote frame if 5 identical bits appear consecutively in the data between the sta...

Page 852: ...or Compare CRC from the received data and the received CRC timing CRC mismatch Receive node CRC field Malformation Detects fields frames in a mixed format Detect mixed format errors Receive node CRC delimiter ACK field End frame Error frame Overload frames ACK error Detects the ACK gap in the sending node Detect recessive bits in the ACK gap Sending node ACK clearance 5 Error frame output timing T...

Page 853: ...node on the bus is activated e g a special case such as when the bus is only connected to the local site the ACK will not be returned even if the data is transferred Therefore duplicate transmission error frames and data In the passive error state the transmit error counter does not increment and the bus shutdown state does not appear Table22 13 Error Status Type type operate The value of the erro...

Page 854: ...t detected when the passive error flag is emitted 2 the Arbitration padding error is detected sending a recessive bit as padding but the dominant bit is detected 8 Nothing has changed Bit error detected while active error flag or overload flag output active error sending node 8 Nothing has changed Bit error detected while active error flag or overload flag output active error receiving node Nothin...

Page 855: ...e operating mode it requests It will remain in initialization mode until the CAN module enters this mode of operation By reading the OPMODE bit of the CnCTRL register you can confirm the completion of the operation mode to be requested During bus shutdown and during bus shutdown recovery sequences the BOFF bit of the CnINFO register is set set to 1 In the bus shutdown recovery sequence the receive...

Page 856: ... the CCERC bit of the CnCTRL register must be set to 1 Therefore the bus shutdown recovery sequence defined by the CAN protocol ISO 11898 is skipped and the module immediately enters operating mode In this case the module is connected to the CAN bus after monitoring 11 consecutive recessive bits For more information see Fig 22 80 Warning This feature is not defined by the CAN protocol ISO 11898 Wh...

Page 857: ...ropagation prop segment and phase segment 1 as defined by the CAN Protocol specification Period 2 is equivalent to phase segment 2 Figure 22 18 Time period settings Data bit time DBT Synchronize segments Propagate segments Phase segment 1 Phase segment 2 Time period 1 TSEG1 Time period 2 TSEG2 Sample Point SPT Segment name The range that can be set A note about setting up the SPECIFICATION for CAN...

Page 858: ...s established Propagate segments Programmable from 1 to 8 or more This segment absorbs the latency of the output buffer CAN bus and input buffer Set the length of this segment so that ACK is returned before phase 1 starts Propagation period output buffer delay 2x CAN bus delay input buffer delay Phase segment 1 Programmable 1 to 8 This segment compensates for errors in data bit times The longer th...

Page 859: ...e synchronization This synchronization is established when the receiving node detects the start of a frame in the inter frame space When a falling edge is detected on the bus TQ represents a synchronous segment and the next segment is a propagation segment In this case synchronization is established regardless of the SJW Figure 22 20 Hard synchronization when the dominant bit is recognized during ...

Page 860: ...oint phase error Negative If the edge is behind the sample point phase error If the phase error is positive by the specified SJW phase segment 1 is longer If the phase error is negative Phase segment 2 is shortened by the specified SJW Due to the difference in baud rate between the sending node and the receiving node the sampling point of the receiving node data moves relatively Figure 22 21 Resyn...

Page 861: ...1 1149 Rev 1 02 22 4 The connection to the target system The microcontroller that integrates CAN must be connected to the CAN bus using an external transceiver Figure22 22 Connect to the CAN bus CAN_L CAN_H Microcontroller with INTEGRATED CAN transceiver CRxD CTxD ...

Page 862: ...nMASK2H The CAN module shields 3 register L CnMASK3L THE CAN module shields 3 register H CNMASK3H THE CAN module shields 4 register L CnMASK4L THE CAN module shields 4 registers H CnMASK4H CAN Module Control Register CnCTRL CAN Module Last Error Code Register CnLEC CAN Module Information Register CnINFO CAN Module Error Count Register CnERC CAN Module Interrupt Enable Register CnIE CAN Module Inte...

Page 863: ...CAN message data byte 4 register m CnMDB4m CAN message data byte 5 register m CnMDB5m CAN message data byte 67 register m CnMDB67m CAN message data byte 6 register m CnMDB6m CAN message data byte 7 register m CnMDB7m CAN message data length register m CnMDLCm CAN message configuration register m CnMCONFm CAN message ID register Lm CnMIDLm CAN message ID register Hm CnMIDHm CAN message control regi...

Page 864: ...nMASK2H There is no definition 0x048H The CAN module masks 3 registers CnMASK3L There is no definition 0x04AH CnMASK3H There is no definition 0x04CH The CAN module masks 4 registers CnMASK4L There is no definition 0x04EH CnMASK4H There is no definition 0x050H THE CAN module controls the registers CnCTRL 0000H 0x052H THE LAST ERROR CODE REGISTER FOR THE CAN MODULE CnLEC 00H 0x053H CAN module inform...

Page 865: ... CnMDLCn0 0000xxxxB 0x109H CAN message configuration register 00 CnMCONF00 There is no definition 0x10AH CAN message ID register 00 CnMIDL00 There is no definition 0x10CH CnMIDH00 There is no definition 0x10EH CAN message control register 00 CnMCTRL00 00x00000 000xx000B 0x110H CAN message data byte 01 register 01 CnMDB0101 There is no definition 0x110H CAN message data byte 0 register 01 CnMDB001 ...

Page 866: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 866 1149 Rev 1 02 definition 0x11CH CnMIDH01 There is no definition 0x11EH CAN message control register 01 CnMCTRL01 00x00000 000xx000B ...

Page 867: ...MDLCn2 0000xxxxB 0x129H CAN message configuration register 02 CnMCONF02 There is no definition 0x12AH CAN message ID register 02 CnMIDL02 There is no definition 0x12CH CnMIDH02 There is no definition 0x12EH CAN message control register 02 CnMCTRL02 00x00000 000xx000B 0x130H CAN message data byte 01 register 03 CnMDB0103 There is no definition 0x130H CAN message data byte 0 register 03 CnMDB003 The...

Page 868: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 868 1149 Rev 1 02 definition 0x13CH CnMIDH03 There is no definition 0x13EH CAN message control register 03 CnMCTRL03 00x00000 000xx000B ...

Page 869: ...MDLCn4 0000xxxxB 0x149H CAN message configuration register 04 CnMCONF04 There is no definition 0x14AH CAN message ID register 04 CnMIDL04 There is no definition 0x14CH CnMIDH04 There is no definition 0x14EH CAN message control register 04 CnMCTRL04 00x00000 000xx000B 0x150H CAN message data byte 01 register 05 CnMDB0105 There is no definition 0x150H CAN message data byte 0 register 05 CnMDB005 The...

Page 870: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 870 1149 Rev 1 02 definition 0x15CH CnMIDH05 There is no definition 0x15EH CAN message control register 05 CnMCTRL05 00x00000 000xx000B ...

Page 871: ...MDLCn6 0000xxxxB 0x169H CAN message configuration register 06 CnMCONF06 There is no definition 0x16AH CAN message ID register 06 CnMIDL06 There is no definition 0x16CH CnMIDH06 There is no definition 0x16EH CAN message control register 06 CnMCTRL06 00x00000 000xx000B 0x170H CAN message data byte 01 register 07 CnMDB0107 There is no definition 0x170H CAN message data byte 0 register 07 CnMDB007 The...

Page 872: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 872 1149 Rev 1 02 definition 0x17CH CnMIDH07 There is no definition 0x17EH CAN message control register 07 CnMCTRL07 00x00000 000xx000B ...

Page 873: ...08 CnMCONF08 There is no definition 0x18AH CAN message ID register 08 CnMIDL08 There is no definition 0x18CH CnMIDH08 There is no definition 0x18EH CAN message control register 08 CnMCTRL08 00x00000 000xx000B 0x190H CAN message data byte 01 register 09 CnMDB0109 There is no definition 0x190H CAN message data byte 0 register 09 CnMDB009 There is no definition 0x191H CAN message data byte 1 register...

Page 874: ...MDLC10 0000xxxxB 0x1A9H CAN message configuration register 10 CnMCONF10 There is no definition 0x1AAH CAN message ID register 10 CnMIDL10 There is no definition 0x1ACH CnMIDH10 There is no definition 0x1AEH CAN message control register 10 CnMCTRL10 00x00000 000xx000B 0x1B0H CAN message data byte 01 register 11 CnMDB0111 There is no definition 0x1B0H CAN message data byte 0 register 11 CnMDB011 The...

Page 875: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 875 1149 Rev 1 02 definition 0x1BCH CnMIDH11 There is no definition 0x1BEH CAN message control register 11 CnMCTRL11 00x00000 000xx000B ...

Page 876: ...nMDLC12 0000xxxxB 0x1C9H CAN message configuration register 12 CnMCONF12 There is no definition 0x1CAH CAN message ID register 12 CnMIDL12 There is no definition 0x1CCH CnMIDH12 There is no definition 0x1CEH CAN message control register 12 CnMCTRL12 00x00000 000xx000B 0x1D0H CAN message data byte 01 register 13 CnMDB0113 There is no definition 0x1D0H CAN message data byte 0 register 13 CnMDB013 Th...

Page 877: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 877 1149 Rev 1 02 definition 0x1DCH CnMIDH13 There is no definition 0x1DEH CAN message control register 13 CnMCTRL13 00x00000 000xx000B ...

Page 878: ...nMDLC14 0000xxxxB 0x1E9H CAN message configuration register 14 CnMCONF14 There is no definition 0x1EAH CAN message ID register 14 CnMIDL14 There is no definition 0x1ECH CnMIDH14 There is no definition 0x1EEH CAN message control register 14 CnMCTRL14 00x00000 000xx000B 0x1F0H CAN message data byte 01 register 15 CnMDB0115 There is no definition 0x1F0H CAN message data byte 0 register 15 CnMDB015 Th...

Page 879: ...BAT32G1x9 user manual Chapter 22 CAN control www mcu com cn 879 1149 Rev 1 02 definition 0x1FCH CnMIDH15 There is no definition 0x1FEH CAN message control register 15 CnMCTRL15 00x00000 000xx000B ...

Page 880: ...TRL R 0 0 0 0 0 0 EFSD Gather 0x001H MBON 0 0 0 0 0 0 0 0x006H CnGMABT W 0 0 0 0 0 0 0 ClearA BTTRG 0x007H 0 0 0 0 0 0 SetA BTCLR SetAB TTRG 0x006H CnGMABT R 0 0 0 0 0 0 ABTCLR ABTTRG 0x007H 0 0 0 0 0 0 0 0 0x008H CnGMABTD 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 0x002H CnGMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0 BAT32G139 n 0 1 BAT32G179 n 0 1 2 Note The actual register address calculation refers to the following ...

Page 881: ...x051H SetC CERC SetAL 0 SetPSMO DE1 SetPSMO DE0 SetOPM ODE2 SetOPM ODE1 SetOPMO DE0 0x050H CnCTRL R CCERC To the VALID PSMODE 1 PSMODE 0 OPMODE 2 OPMODE 1 OPMODE 0 0x051H 0 0 0 0 0 0 RSTAT TSTAT 0x052H CnLEC W 0 0 0 0 0 0 0 0 0x052H CnLEC R 0 0 0 0 0 LEC2 LEC1 LEC0 0x053H CnINFO 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 0x054H CnERC TEC 7 0 0x055H REPS REC 7 0 0x056H CnIE W 0 0 Clear CIE5 Clear CIE4 Clea...

Page 882: ...0 Clear ROVF 0x061H 0 0 0 0 0 0 0 0 0x060H CnRGPT R 0 0 0 0 0 0 RHPM ROVF 0x061H RGPT 7 0 0x062H CnLOPT LOPT 7 0 0x064H CnTGPT W 0 0 0 0 0 0 0 Clear TOVF 0x065H 0 0 0 0 0 0 0 0 0x064H CnTGPT R 0 0 0 0 0 0 THPM TOVF 0x065H TGPT 7 0 0x066H CnTS W 0 0 0 0 0 ClearT SLOCK Clear TSSEL Clear TSEN 0x067H 0 0 0 0 0 SetT SLOCK SetT SSEL TSE N Set 0x066H CnTS R 0 0 0 0 0 TSLOCK TSSEL TSEN 0x067H 0 0 0 0 0 0 ...

Page 883: ...H CnMDB67m Message data byte 6 0x1x7H Message data byte 7 0x1x6H CnMDB6m Message data byte 6 0x1x7H CnMDB7m Message data byte 7 0x1x8H CnMDLCm 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 0x1x9H CnMCONFm OWS Rtr MT2 MT1 MT0 0 0 MA0 0x1xAH CnMIDLm ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1xBH ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 0x1xCH CnMIDHm ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 0x1xDH IDE 0 0 ID28 ID27 ID26 ID25...

Page 884: ...CnTGPT CAN Module Timestamp Register CnTS CAN Message Control Register CnMCTRLm Remark m 0 to 15 BAT32G139 n 0 1 BAT32G179 n 0 1 2 All 16 bits in the above registers can be read by common methods Use the procedure described in Figure22 23to set or clear the lower 8 bits in these registers The setting or clearance of the lower 8 bits in the above register is performed in conjunction with the higher...

Page 885: ...ote n 0 to 7 22 7 Control registers Note m 0 to 15 22 7 1 Peripheral clock selection register PER0 PER2 The PER0 2 register is a register that is set to allow or disable clocking to each peripheral hardware Reduce power consumption and noise by stopping clocking hardware that is not in use To use the CAN function theCANn EN must be placed at 1 For details see 4 3 8 Perimeter Allow Registers 0 1 2 ...

Page 886: ...story list registers Note 1 When the MBON bit is cleared to 0 the software accesses the packet buffer CnMDB0m CnMDB1m CnMDB01m CnMDB2m CnMDB3m CnMDB23m CnMDB4m CnMDB5m CnMDB45m CnMDB6m CnMDB7m CnMD B67m CnMDLCm CnMCONFm CnMIDLm CnMIDHm andCnMCTRLm Or send history or receive history registers CnLOPT CnTGPT CnLIPT and CnRGPT are disabled 2 This bit is read only when MBON is 0 write to it 1 the value...

Page 887: ...to 0 and the force close request is invalid When performing DMA requests for forced shutdown may be ignored Be sure to read the EFSD bits and confirm that force shutdown is enabled before issuing a forced shutdown request If force shutdown cannot be enabled because DMA is being performed it is recommended that you temporarily stop DMA Gather Global operating mode bits 0 CAN module operation is dis...

Page 888: ... Selection Register Format CnGMCS CnGMCS 7 6 5 4 3 2 1 0 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN Module System Clock fCANMOD 0 0 0 0 fCAN 1 0 0 0 1 fCAN 2 0 0 1 0 fCAN 3 0 0 1 1 fCAN 4 0 1 0 0 fCAN 5 0 1 0 1 fCAN 6 0 1 1 0 fCAN 7 0 1 1 1 fCAN 8 1 0 0 0 fCAN 9 1 0 0 1 fCAN 10 1 0 1 0 fCAN 11 1 0 1 1 fCAN 12 1 1 0 0 fCAN 13 1 1 0 1 fCAN 14 1 1 1 0 fCAN 15 1 1 1 1 fCAN 16 default Note fCA...

Page 889: ... 0 0 0 ABTCLR ClearA BTTRG Note Before changing the normal operating mode of ABT to initialization mode make sure that the CnGMABT register is set to the default value 0000H and confirm that the CnGMABT register must have been initialized to the default value 0000H a read ABTCLR Automatic block transfer clear status bits 0 Clearing the autotransport engine is complete 1 The autotransfer engine is ...

Page 890: ...k transfer engine clears the request bits 0 The automatic block transfer engine is idle or in operation 1 Request to clear Automatic Block Transfer When the automatic block transfer engine is cleared automatic block transfer starts from the packet cache 0 after setting ABTTRG to 1 SetABTTRG ClearABTTRG Automatic block transfer start bit 0 1 Request to stop automatic block transfer 1 0 Request to s...

Page 891: ...4 3 2 1 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 ABTD3 ABTD2 ABTD1 ABTD0 Data frame interval unit Data Bit Time DBT for automatic block transfer 0 0 0 0 0 DBT default 0 0 0 1 25 DBT 0 0 1 0 26 DBT 0 0 1 1 27 DBT 0 1 0 0 28 DBT 0 1 0 1 29 DBT 0 1 1 0 210 DBT 0 1 1 1 211 DBT 1 0 0 0 212 DBT Other values forbid Note 1 When ABTTRG is 1 do not change the contents of cngMABTD 2 The time at which ABT packets ar...

Page 892: ...MASKaH registers expand the number of message caches that enter the same packet cache by comparing the masked portion of the packet ID and invalidating the ID of the masked portion Figure 22 29 Format of the CAN module mask register CnMASKaL CnMASKaH a 1 2 3 or 4 1 2 CAN module shield 1 register CnMASK1L CnMASK1H CAN module shield 2 registers CnMASK2L CnMASK2H ...

Page 893: ... of the packet buffer set by CMID0 through CMID28 are compared to the ID bits of the received packet frames 1 The ID bits of the packet buffer set by CMID0 through CMID28 are not compared to the ID bits of the received packet frames they are masked Note Masking is always determined by the ID length of 29 bits If the mask is assigned to a message with a standard ID cmID 0 to CMID 17 bits are ignore...

Page 894: ...d b write a read RSTAT Receive status bits 0 The receive is stopped 1 Receive is in progress Note The RSTAT bit is set to 1 under the following conditions timing The SOF bit of the received frame is detected Arbitration loss occurs in the transmission frame The RSTAT bit is cleared to 0 under the following conditions timing The second bit in interframe space detects recessive bits The transition t...

Page 895: ... mode to operating mode the CCERC bit is set to 1 4 When the CCERC bit is set to 1 immediately after entering INIT mode from self test mode the received data may be corrupted To the Sets the bit of the action when the Arbitration is lost 0 When a Arbitration loss occurs in single time mode no retransmission is performed 1 Perform a retransmission when an arbitral loss occurs in single shot mode No...

Page 896: ...e bus condition bus idle The software can check the actual status by reading the PSMODE OPMODE2 OPMODE1 OPMODE0 Mode of operation 0 0 0 There is no operating mode selected CAN mode is in initialization mode 0 0 1 Normal mode of operation 0 1 0 There is a normal operating mode of automatic block transfer normal operating mode with ABT 0 1 1 Receive mode only 1 0 0 Single shot mode 1 0 1 Self test m...

Page 897: ...ues PSMODE0 does not change SetPSMODE1 ClearPSMODE1 Set the PSMODE1 bit 0 1 PSMODE1 clear 0 1 0 PSMODE1 is set to 1 Other values PSMODE1 does not change SetOPMODE0 ClearOPMODE0 Set the OPMODE 0 bit 0 1 OPMODE0 clear 0 1 0 OPMODE0 1 Other values OPMODE0 does not change SetOPMODE1 ClearOPMODE1 Set the OPMODE1 bit 0 1 OPMODE1 clear 0 1 0 OPMODE1 is set to 1 Other values OPMODE1 does not change SetOPM...

Page 898: ... than 00H to the CnLEC register through the software the access will be ignored LEC2 LEC1 LECn Last CAN protocol error message 0 0 0 No errors 0 0 1 Fill errors 0 1 0 Malformation 0 1 1 ACK error 1 0 0 Bit error the CAN module attempts to transmit recessive bits as part of the transmitted message except for the Arbitration field but the value on the CAN bus is the dominant bit 1 0 1 Bit error the ...

Page 899: ...sion counter value equal to or greater than 256 TECS1 TECS0 Send error counter status bits 0 0 The value of the Send Error counter is less than the warning level 96 0 1 Send the value of the error counter in the warning range 96 to 127 1 0 There is no definition 1 1 Sends the value of the error counter within the passive error or bus shutdown state 128 RECS1 RECS0 Receive error counter status bits...

Page 900: ...in the passive error range 128 REC6 RECn Receive error counter bits 0 127 The number of errors received These bits reflect the status of the receive error counter The number of errors is defined by the CAN protocol Note The REC 6 0 of the receive error counter is not valid in the receive passive error state RECS 1 0 11B TEC7 TECn Send error counter bits 0 255 The number of transmission errors Thes...

Page 901: ...rite a read CIE5 CIE0 CAN module interrupt enable bit 0 The interrupt output corresponding to the cnINTS 5 0 bit of the interrupt status register is disabled 1 The interrupt output corresponding to the cnINTS 5 0 bit of the interrupt status register is enabled b write SetCIE5 ClearCIE5 Set the CIE5 bit 0 1 CIE5 clear 0 1 0 CIE5 set 1 Other values CIE5 has not changed SetCIE4 ClearCIE4 Set the CIE4...

Page 902: ...E3 bit 0 1 CIE3 clear 0 1 0 CIE3 set 1 Other values CIE3 has not changed SetCIE2 ClearCIE2 Set the CIE2 bit 0 1 CIE2 clear 0 1 0 CIE2 set 1 Other values CIE2 has not changed SetCIE1 ClearCIE1 Set the CIE1 bit 0 1 CIE1 clear 0 1 0 CIE1 to 1 Other values CIE1 has not changed SetCIE0 ClearCIE0 Set the CIE0 bit 0 1 CIE0 clear 0 1 0 CIE0 to 1 Other values CIE0 has not changed ...

Page 903: ... interrupt CINTS3 CAN protocol error interrupted CINTS2 The CAN error status is interrupted CINTS1 A valid packet frame receives a completion interrupt to the packet buffer m CINTS0 Interrupt of packet frame transmission from message buffer m normally completed 1 The CINTS5 bit is set only when the CAN module wakes up from CAN sleep mode via CAN bus operation When the software releases the CAN sle...

Page 904: ... basic system clock fTQ 0 fCANMOD 1 1 fCANMOD 2 n fCANMOD n 1 255 fCANMOD 256 default Figure 22 37 CAN global clock CAN Global Module Clock Selection Register CnGMCS CAN Module Bit Rate Scaling Register CnBRP Note The CnBRP register can only be written in initialization mode Note fCAN Provides a clock fMAIN to CAN fCANMOD CAN module system clock fTQ CAN protocol layer base system clock 0 0 0 0 CCP...

Page 905: ...s used to control the data bit time of the baud rate Figure 22 38 CAN Module Bit Rate Register Format CnBTR 1 2 SJW1 SJW0 Synchronize the length of the jump width 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ default TSEG22 TSEG21 TSEG20 The length of the time period 2 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ default ...

Page 906: ...TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1 0 7TQ 0 1 1 1 8TQ 1 0 0 0 9TQ 1 0 0 1 10TQ 1 0 1 0 11TQ 1 0 1 1 12TQ 1 1 0 0 13TQ 1 1 0 1 14TQ 1 1 1 0 15TQ 1 1 1 1 16TQ default 1 These settings must be performed when the CnBRP register is 00H Note TQ 1 fTQ fTQ CAN protocol layer base system clock Figure 22 39 Data bit time Data Bit Time DBT Synchronize segments Propagate segments Phase segment 1 Phase segment 2 ...

Page 907: ...er CnLIPT 0 to 15 When the CnLIPT register is read the contents of the element indexed by the last input pointer LIPT of the received history list are read These indicate the number of message buffers where the data frame or remote frame was last stored Note If the data frame or remote frame is never stored in the message buffer the read value of the CnLIPT register is undefined If the RHPM bit of...

Page 908: ... is 1 the reading values from RGPT0 to RGPT7 are invalid ROVF1 Receives history list overflow bits 0 All packet buffer numbers that have not yet been read are retained The packet cache numbers received and stored in all new data frames or remote frames have been recorded to the receive history list the receive history list has an empty element 1 At least 23 entries have been stored since the host ...

Page 909: ... Output Pointer LOPT 0 to 15 When the CnLOPT register is read the contents of the element indexed by the last out pointer LOPT of the received history list are read These indicate the number of message buffers to which the data frame or remote frame was last transmitted Note If a data frame or remote frame is never transmitted from the packet buffer the value read from the CnLOPT register is undef...

Page 910: ...d TOVF Send history list overflow bit 0 All packet buffer numbers that have not yet been read are retained All numbers of the message buffer to which the new data frame or remote frame is transmitted are recorded to the transmission history list the transmission history list has an empty element 1 At least 7 entries i e read CnTGPT have been stored since the host processor last served THL The firs...

Page 911: ...ode with ABT the lock function of the timestamp function must not be used a read TSLOCK Timestamp lock function enables bits 0 The timestamp lock feature stops Each time the selected timestamp capture event occurs the TSOUT signal is toggled 1 The timestamp lock feature enables Each time the selected timestamp capture event occurs the TSOUT signal is toggled However when the data frame is correctl...

Page 912: ...ipping operation is prohibited 1 TSOUT signal flip operation enables Note The signal TSOUT is output from the CAN macro to the timer resource depending on the implementation See Chapter 6 Universal Timer Units b write SetTSLOCK ClearTSLOCK TSLOCK setting bit 0 1 TSLOCK clear 0 1 0 TSLOCK set 1 Other values TSLOCK does not change SetTSSEL ClearTSSEL TSSEL setting bit 0 1 TSSEL clear 0 1 0 TSSEL set...

Page 913: ... 6 5 4 3 2 1 0 CnMDB0m MDATA07 MDATA06 MDATA05 MDATA04 MDATA03 MDATA02 MDATA01 MDATA00 7 6 5 4 3 2 1 0 CnMDB1m MDATA17 MDATA16 MDATA15 MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 7 6 5 4 3 2 1 0 CnMDB2m MDATA27 MDATA26 MDATA25 MDATA24 MDATA23 MDATA22 MDATA21 MDATA20 7 6 5 4 3 2 1 0 CnMDB3m MDATA37 MDATA36 MDATA35 MDATA34 MDATA33 MDATA32 MDATA31 MDATA30 7 6 5 4 3 2 1 0 CnMDB4m MDATA47 MDATA46 MDATA45 M...

Page 914: ...DB23m MDATA 2315 MDATA 2314 MDATA 2313 MDATA 2312 MDATA 2311 MDATA 2310 MDATA 239 MDATA 238 7 6 5 4 3 2 1 0 MDATA 237 MDATA 236 MDATA 235 MDATA 234 MDATA 233 MDATA 232 MDATA 231 MDATA 230 15 14 13 12 11 10 9 8 CnMDB45m MDATA 4515 MDATA 4514 MDATA 4513 MDATA 4512 MDATA 4511 MDATA 4510 MDATA 459 MDATA 458 7 6 5 4 3 2 1 0 MDATA 457 MDATA 456 MDATA 455 MDATA 454 MDATA 453 MDATA 452 MDATA 451 MDATA 450...

Page 915: ...hibited If these bits are set during transmission 8 bytes of data are transferred regardless of the DLC value set when the data frame was transmitted However the DLC that is actually transmitted to the CAN bus is the DLC value set to this register 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1The data and DLC values actually transmitted to the CAN bus are as follows The type of frame sent The...

Page 916: ...ing message buffer generate interrupts set DN flags MDLC 3 0 bit updates and recorded in the receive history list Rtr Remote frame request bit 1 0 Send a data frame 1 Sends a remote frame The 1 RTR bit specifies the type of packet frame transferred from a packet buffer defined as a transmit packet buffer Even if a valid remote frame has been received the RTR of the transmitted packet buffer for th...

Page 917: ...ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13 12 11 10 9 8 CnMIDHm IDE 0 0 ID28 ID27 ID26 ID25 ID24 7 6 5 4 3 2 1 0 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE The format mode specifies the bit 0 Standard format mode ID18 to ID28 11 bits 1 1 Extended format mode ID0 to ID28 29 bits 1 ID0 to ID17 bits are not used ID0 to ID28 Message ID ID18 through ID28 11 bit standard...

Page 918: ...receive and store 1 The CAN module is updating the message buffer receive and store Note The MUC bit is undefined until the first receive and store is made MOW Message caching overrides the status bit 0 Newly received data frames do not overwrite the packet buffer 1 The newly received data frame overwrites the packet buffer Note Even if a remote frame is received and stored in the transmit message...

Page 919: ...t write access to RDY TRQ DN and MOW bits is ignored The CAN module can write to the packet buffer Note 1 Do not clear the RDY bit 0 during message transmission Clear the RDY bit 0 as per the transfer abort to redefine the packet buffer 2 When the RDY bit is not cleared although it has been cleared clear again 3 Before writing to the packet buffer register ensure that the RDY bit is cleared This a...

Page 920: ...om other nodes or transmitting dissipative packets even if the TRQ bit is set to 1 the transmission may not start immediately Even if the TRQ bit is cleared to 0 the transfer is not aborted If a message is being transmitted the transmission continues until the transmission is complete successful or unsuccessful SetRDY ClearRDY RDY setting bit 0 1 RDY clear 0 1 0 RDY set to 1 Other values RDY does ...

Page 921: ...selection CTxD0 CRxD0 0 P02 P03 1 P51 P50 22 7 26 Port mode registers 0 4 5 6 PM0 4 5 6 The PMx register is used to set port x as input or output When using the P02 CTxD0 or P51 CTxD0 or P64 CTxD1 or P46 CTxD2 pins for serial data output clear the PM02 or PM51 or PM64 or PM46 bits to 0 and set the output latch of the P02 or P51 or P64 or P46 to 1 When using the P03 CRxD0 or P50 CRxD0 or P65 CRxD1 ...

Page 922: ...er means that when a packet is received or transmitted the ID and control information of the packet buffer is changed without affecting other send receive operations 1 Redefine the message cache in initialization mode Put the CAN module into initialization mode once and then change the ID and control information of the packet buffer in initialization mode After changing the ID and control informat...

Page 923: ...st received and stored in the message buffer after redefining ID and IDE Whether it is stored after the packet buffer is redefined ID and IDE If it is not stored after redefining ID and IDE redefine the packet buffer 2 When sending a message the transmission priority is checked against the ID IDE and RTR bits set to each sending message buffer Select the transmission packet buffer with the highest...

Page 924: ...2 8 5 Resets the CAN Module Error Counter cnERC If you need to reset the CAN module error counter CnERC and the CAN module information register CnINFO when reinitializing or forced recovery from the bus shutdown state set the CCPERC bit of the CnCTRL register to 1 in initialization mode When this bit is set to 1 the CAN module error counter CnERC and the CAN module information register CnINFO will...

Page 925: ...even if the packet buffer has not yet received the packet and the message is already in the unmasked receive packet buffer In other words when set to store messages in two or more packet buffers with different priorities the message buffer with the highest priority always stores messages Messages are not stored in lower priority packet buffers This also applies when the message buffer with the hig...

Page 926: ...ffer CnMCTRLm register is set See Figure 22 53 The received history list is also updated before the stored procedure In addition during the stored procedure MUC_1 the RDY bit of the CnMCTRLm register of the message buffer is locked to avoid coincidental data WR through the CPU Note that when the CPU accesses the packet buffer the stored process may be disturbed delayed Figure 22 53 The DN and MUC ...

Page 927: ...ed data frames or remote frames Each time the message buffer number is read from the CnRGPT register the RGPT pointer is automatically incremented If the value of the RGPT pointer matches the value of the LIPT pointer the RHPM bit of the CnRGPT register receive history list pointer matches is set to 1 This indicates that the unread packet buffer number in THEHL is not retained If a new message buf...

Page 928: ...eceived RHL is full ROVF is configured last received message pointer LIPT received historical list RHL acquire pointer from received message historical list RGPT message buffer 8 message buffer 4 message buffer 3 received historical list RHL message buffer 15 message buffer 11 message buffer 10 message buffer 8 message buffer 4 message buffer 3 message buffer 1 message buffer 9 message buffer 5 la...

Page 929: ... ID18 x 0 0 0 1 x 1 x x x x x Leave it alone 2 identifier is configured into packet cache 14 example Use the CAN 0 message ID registers L14 and H14 CnMIDL14 and CnMIDH14 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x x x x ID6 ID5 ID4 ID3 ID2 ID1 ID0 x x x x x x x IDs from ID25 to ID27 are cleared as ...

Page 930: ... to 0 disable interrupt and the IE bit in packet buffer k 1 is set to 1 interrupt is enabled In this case a receive completion interrupt occurs when a message is received and stored in the message buffer k 1 indicating that the MBRB is full Alternatively by clearing the IE bits of the packet buffer 0 to k 3 and setting the IE bits of the packet buffer k 2 you can issue a warning that the MBRB is a...

Page 931: ...the CnMDLCm register stores the received DLC value The Data Intervals from CnMDATA0m to CnMDATA7m are not updated saving pre receive data The DN bit of the CnMCTRLm register is set at 1 The CNINTS register s CINTS1 bit is set to 1 if the IE bit in the received and stored message buffer registers cnMCTRLm is set to 1 Output Receive Completion Interrupt INTCREC if the IE bit in the message buffer re...

Page 932: ...he message which eliminates the need for software priority control The send priority is controlled by an identifier ID Figure 22 55 Example of message handling message No message waiting to be transmitted CAN module will transmit messages based on following order 1 message 6 2 message 1 3 Message 8 4 Message 5 5 message2 After sending a packet search sends the highest priority send message with th...

Page 933: ...G is set to 1 in normal operating mode with ABT the TRQ bit of only one packet cache in the ABT packet cache group is set to 1 If the ABT pattern is triggered by the ABTTRG bit one of the TRQ bits in the ABT region is set to 1 buffers 0 to 7 In addition to this TRQ bit the application can request other TX packet buffer transfers that are not part of the ABT region set the TRQ to 1 In this case the...

Page 934: ...ointer is automatically incremented If the value of the TGPT pointer matches the value of the LOPT pointer the THPM bit of the CnTGPT register transfer history list pointer matches is set to 1 This indicates that no unread packet buffer numbers are reserved in the TRL If a new message buffer number is logged the LOPT pointer will be incremented and since its value no longer matches the value of th...

Page 935: ...mpletion overflow occurs event message 8 5 6and 10 transmission completion acquire pointer from transmit histoical list TGPT THL full 1 TOVF is set TOVF 1 LOPT is locked acquire pointer from transmit histoical list TGPT acquire pointer from transmit histoical list TGPT TOVF 1 LOPT is locked message buffer 7 message buffer 2 message buffer 9 message buffer 6 message buffer 5 message buffer 8 messag...

Page 936: ...interval of the transfer request TRQ that is automatically set when performing a continuous transfer The delay time to insert is defined by the CnGMABTD register The unit of delay time is DBT Data Bit Time DbT depends on the setting of the CnBRP and CnBTR registers In the transfer object within the ABT region the priority of the transport ID is not evaluated Data from packet buffers 0 to 7 are tra...

Page 937: ...time is not inserted in the time interval for the ABT transmission request CnGMABTD 00H is automatically set the message other than the ABT message may not depend on the priority of the ABT message 7 When ABTTRG 1 do not clear the RDY bit to 0 8 If a packet is received from another node while the normal mode of operation with ABT is active the TX packet in the ABT region may be transmitted with a ...

Page 938: ...this may not be possible if the transfer is aborted by clearing the RDY bits When the normal mode of operation of ABT is restored after ABT abort and the ABTTRG bit is set to 1 the next ABT packet buffer to be transmitted can be determined from the following table ABT packet caching status TRQ Abort after a successful transfer Aborted after error transmission Setting 1 The next message cache for t...

Page 939: ... if the interrupt is in sleep mode the interrupt must use the MBON flag to check access to the packet buffer as well as to the receive history list register If any of the above conditions are not met the CAN module will run as follows If the request enters CAN sleep mode from initialization mode the CAN sleep mode conversion request is ignored and the CAN module remains in initialization mode If t...

Page 940: ...PU turns off the CAN clock while in CAN sleep mode Even then the CAN sleep mode will not be released and the PSMODE 1 0 will continue to be 01B unless the clock for CAN is provided again In addition to this received messages will not be received afterwards 2 If the falling edge on the CAN receive pin CRxD is detected in the state where the CAN clock is provided the PSMODE0 bit needs to be cleared ...

Page 941: ...ot be Acknolwdgeed however in the state where the CAN clock is provided the PSMODE0 bit needs to be cleared by software after a bus change occurs on the CAN receive pin CRxD 2 CAN stop mode status After entering CAN stop mode the CAN module is in one of the following states The internal operating clock stops with minimal power consumption To wake up the CAN module data can be written to the PSMODE...

Page 942: ...e CAN receive pin CRxD detects a bus change The CPU responds to INTCnWUP and can release its own power saving mode and return to normal operation mode To further reduce the CPU s power consumption the internal clock including the clock of the CAN module may stop In this case after the CAN module is placed in CAN sleep mode the operating clock provided to the CAN module will stop The CPU then enter...

Page 943: ...the packet cache 2 CINTS1Note CnINTS CIE1Not e Miss INTCnREC The message cache receives a valid message frame 3 CINTS2 CnINTS CIE2 Miss INTCnERR CAN Module Status Error Interrupt Supplement 1 4 CINTS3 CnINTS CIE3 Miss CAN module protocol error interrupt supplement 2 5 CINTS4 CnINTS CIE4 Miss CAN module Arbitration loss interrupt 6 CINTS5 CnINTS CIE5 Miss INTCnWUP The CAN module wakes up interrupts...

Page 944: ...r data frame or the transmit message buffer remote frame Indicate a valid receive event by setting the VALID bit of cnCTRL register 1 Figure 22 57 CAN mode only receives terminal connections in receive mode In receive only mode message frames cannot be transmitted from the CAN module to the CAN bus Packet caching is defined as sending a transition request for packet caching to be pending In receiv...

Page 945: ...pass mode disables retransmissions that abort packet frame transmissions based on the AL bit setting of the CnCTRL register When the AL bit is cleared to 0 the Arbitration is lost and the retransmission is disabled when an error occurs If the AL bit is set to 1 retransmission is disabled when an error occurs but retransmission is enabled when Arbitration is lost Therefore the following event is de...

Page 946: ...level If the upper descending edge of the CAN receive pin CRxD is detected after the CAN module enters CAN sleep mode from self test mode the module is released from CAN sleep mode in the same way as other modes of operation However to release the CAN sleep mode the PSMODE0 bit needs to be cleared by software after the falling edge on the CAN receive pin CRxD is detected in the state where the CAN...

Page 947: ...atic Block Transfer ABT Sets the VALID bit Store data to the message cache Initialization mode not not not not not not not Normal operating mode be be be be not be be Normal mode of operation with ABT be be be be be be be Receive mode only not not not not not be be Single shot mode be be be No Note1 not be be Self test mode e It s Note2 It s Note2 It s Note2 It s Note2 not It s Note2 It s Note2 No...

Page 948: ...vent by reading the captured value that is the timestamp of the message received from the CAN bus The TSOUT signal can be selected from the following two event sources and specified by the TSSEL bit of the CnTS register SOF event frame start TSSEL 0 EOF event last bit of the end frame TSSEL 1 TSOUT signal enable requires setting the TSEN bit of the CnTS register to 1 Figure 22 59 Timing diagram of...

Page 949: ...ion with ABT it is impossible to receive data frames in message buffer 0 because message buffer 0 must be set to send message buffer Therefore in this mode of operation the TSLOCK bit cannot be used to stop the function of toggling the TSOUT bit By switching the input source using TMOS1 the capture trigger signal TSOUT of CAN controller channel 0 can be input to channel 2 of timer array unit 0 wit...

Page 950: ...QSPT TSEG1 1TQ b 8TQ DBT Data Bit Time 25TQ DBT TSEG1 TSEG2 1TQ TSEG2 SPT c 1TQ SJW Synchronous Jump Width 4TQSJW DBT SPT d 4TQ TSEG1 16TQ 3 TSEG1 3 0 15 setting value e 1TQ TSEG2 8TQ 0 setting value for TSEG2 2 0 7 Note TQ 1 fTQ fTQ CAN protocol layer base system clock TSEG1 3 0 Bits 0 to 3 of the CAN bit rate register CnBTR TSEG2 2 0 Bits 8 to 10 of the CAN bit rate register CnBTR Table22 22show...

Page 951: ... 9 6 6 1110 101 72 7 22 1 11 5 5 1111 100 77 3 21 1 4 8 8 1011 111 61 9 21 1 6 7 7 1100 110 66 7 21 1 8 6 6 1101 101 71 4 21 1 10 5 5 1110 100 76 2 21 1 12 4 4 1111 011 81 0 20 1 3 8 8 1010 111 60 0 20 1 5 7 7 1011 110 65 0 20 1 7 6 6 1100 101 70 0 20 1 9 5 5 1101 100 75 0 20 1 11 4 4 1110 011 80 0 20 1 13 3 3 1111 010 85 0 19 1 2 8 8 1001 111 57 9 19 1 4 7 7 1010 110 63 2 19 1 6 6 6 1011 101 68 4...

Page 952: ... 16 1 3 6 6 1000 101 62 5 16 1 5 5 5 1001 100 68 8 16 1 7 4 4 1010 011 75 0 16 1 9 3 3 1011 010 81 3 16 1 11 2 2 1100 001 87 5 16 1 13 1 1 1101 000 93 8 15 1 2 6 6 0111 101 60 0 15 1 4 5 5 1000 100 66 7 15 1 6 4 4 1001 011 73 3 15 1 8 3 3 1010 010 80 0 15 1 10 2 2 1011 001 86 7 15 1 12 1 1 1100 000 93 3 14 1 1 6 6 0110 101 57 1 14 1 3 5 5 0111 100 64 3 14 1 5 4 4 1000 011 71 4 14 1 7 3 3 1001 010 ...

Page 953: ...2 2 0110 001 80 0 10 1 7 1 1 0111 000 90 0 9 1 2 3 3 0100 010 66 7 9 1 4 2 2 0101 001 77 8 9 1 6 1 1 0110 000 88 9 8 1 1 3 3 0011 010 62 5 8 1 3 2 2 0100 001 75 0 8 1 5 1 1 0101 000 87 5 7Note 1 2 2 2 0011 001 71 4 7Note 1 4 1 1 0100 000 85 7 6Note 1 1 2 2 0010 001 66 7 6Note 1 3 1 1 0011 000 83 3 5Note 1 2 1 1 0010 000 80 0 4Note 1 1 1 1 0001 000 75 0 Note Setting DBT with a value of 7 or less is...

Page 954: ...0 16 1 11 2 2 1100 001 87 5 500 1 00000000 16 1 13 1 1 1101 000 93 8 500 2 00000001 8 1 1 3 3 0011 010 62 5 500 2 00000001 8 1 3 2 2 0100 001 75 0 500 2 00000001 8 1 5 1 1 0101 000 87 5 250 2 00000001 16 1 1 7 7 0111 110 56 3 250 2 00000001 16 1 3 6 6 1000 101 62 5 250 2 00000001 16 1 5 5 5 1001 100 68 8 250 2 00000001 16 1 7 4 4 1010 011 75 0 250 2 00000001 16 1 9 3 3 1011 010 81 3 250 2 00000001...

Page 955: ...001 100 68 8 83 3 6 00000101 16 1 7 4 4 1010 011 75 0 83 3 6 00000101 16 1 9 3 3 1011 010 81 3 83 3 6 00000101 16 1 11 2 2 1100 001 87 5 83 3 8 00000111 12 1 5 3 3 0111 010 75 0 83 3 8 00000111 12 1 7 2 2 1000 001 83 3 83 3 12 00001011 8 1 3 2 2 0100 001 75 0 83 3 12 00001011 8 1 5 1 1 0101 000 87 5 33 3 10 00001001 24 1 7 8 8 1110 111 66 7 33 3 10 00001001 24 1 9 7 7 1111 110 70 8 33 3 12 0000101...

Page 956: ...6 3 500 2 00000001 16 1 3 6 6 1000 101 62 5 500 2 00000001 16 1 5 5 5 1001 100 68 8 500 2 00000001 16 1 7 4 4 1010 011 75 0 500 2 00000001 16 1 9 3 3 1011 010 81 3 500 2 00000001 16 1 11 2 2 1100 001 87 5 500 2 00000001 16 1 13 1 1 1101 000 93 8 500 4 00000011 8 1 3 2 2 0100 001 75 0 500 4 00000011 8 1 5 1 1 0101 000 87 5 250 4 00000011 16 1 3 6 6 1000 101 62 5 250 4 00000011 16 1 5 5 5 1001 100 6...

Page 957: ...81 3 83 3 12 00001011 16 1 11 2 2 1100 001 87 5 83 3 16 00001111 12 1 5 3 3 0111 010 75 0 83 3 16 00001111 12 1 7 2 2 1000 001 83 3 83 3 24 00010111 8 1 3 2 2 0100 001 75 0 83 3 24 00010111 8 1 5 1 1 0101 000 87 5 33 3 30 00011101 24 1 7 8 8 1110 111 66 7 33 3 30 00011101 24 1 9 7 7 1111 110 70 8 33 3 24 00010111 20 1 9 5 5 1101 100 75 0 33 3 24 00010111 20 1 11 4 4 1110 011 80 0 33 3 30 00011101 ...

Page 958: ...er Please refer to the process of development in this chapter Note m 0 to 15 Fig 22 61 initialize Set the CnGMCS register Set up CnGMCTRL Register set GOM 1 Set the CnBRP register the CnBTR register Set the CnIE registers Set the CnMASK register Initialize the packet cache Set up CnCTRL register set OPMODE remark OPMODE Normal operating mode normal operating mode accompaniment Abbot receive only m...

Page 959: ...er Set the CnIE registers Set the CnMASK register Initialize the message buffer Note After the CAN module is set to initialization mode do not immediately set it to another operating mode If you need to immediately set the module to a different operating mode visitCnCTRL and CnGMCTRLRegisters other than registers for example setting a message buffer Remarks OPMODE normal operation mode normal oper...

Page 960: ... to the settings below for unused packet caching Clear the RDY TRQ and DN bits of the CnMCTRLm register to 0 Clear the MA0 bit of the CnMCONFm register to 0 Clear RDY bit Set the C0MCONFm register Set the C0MeDHm register C0MeDlm register Clear the C0MDBm register Set the C0MCTRLm register Set the RDY bit Begin no t RDY 1 yes no t RDY 0 yes no t Send message cache yes Set the C0MDLCm register end ...

Page 961: ... cache processing CnMCONFm register MT 2 0 bits 001B to 101B Fig 22 64 Packet cache redefinition yes Note2 Wait for 4 CAN data bits Set up message caching Set the RDY bit Note 1 Acknowledgement of receipt of the message is due to the fact that the message has been fully receivedRDYBits are set 2 Avoid redefining the packet buffer during a stored packet receive operation by waiting for an additiona...

Page 962: ...redefinition during sending Send abort processing Clear the RDY bit Set the C0MDATAxm register Set the C0MDLCm register Clear C0MCONFm registerRTR bit Set upC0MeDlm and C0MIDHmregister Set the C0MDLCm register Set theC0MCONFm register RTR bit Set upC0MeDlm and C0MeDHm register Set the RDY bit Wait for 1CAN data bit Set the TRQ bit Begin RDY 0 not yes Data frames Data frame or remote frame Remote f...

Page 963: ...r RDY settings 2 The RDY bit and the TRQ bit cannot be set at the same time Clear the RDY bit Data frame or remote frame Set the C0MDATAxm register Set the C0MDLCm register Clear the C0MCONFm register RTR bit Set upC0MeDLm and C0MeDHmregister Set the C0MDLCm register Set the C0MCONFm register RTR bit Set upC0MIDlm and C0MIDHm register Set the RDY bit Set the TRQ bit Begin TRQ 0 no t yes RDY 0 no t...

Page 964: ...B Fig 22 67 Abbot Packet sending processing Note After the TSTAT bit is cleared to 0 the ABTTRG bit should be set to 1 The TSTAT bit must be checked continuously and the ABTTRG bit set to 1 Note This processing using the normal operating mode of ABS can only be applied to packet buffers 0 to 7 For packet buffers other than ABT packet buffers see Figure 22 66 Set the CnMDATAxm register Set the CnMD...

Page 965: ...a pending sleep mode If MBON is detected to be cleared the result must be discarded and the operation processed again after MBON is set up again It is recommended to remove some sleep mode requests before handling TX interrupts Read the C0LOPT register Clear the RDY bit Data frame or remote frame Set the RDY bit Begin Send completes interrupt processing RDY 0 no t yes Data frames Remote frames Set...

Page 966: ... operation processed again after MBON is set up again It is recommended to remove some sleep mode requests before handling TX interrupts 2 If TOVF is set the transmission history list is inconsistent Consider scanning all configured transfer buffers to complete the transfer Read the C0TGPT register Clear TOVF bit Clear the RDY bit Set upC0MDATAxmregister Set upC0MDLCmregister clear C0MCONFm regist...

Page 967: ... result must be discarded and the operation processed again after MBON is set up again 2 If TOVF is set the transmission history list is inconsistent Consider scanning all configured transfer buffers to complete the transfer Set the RDY bit Set the TRQ bit Set upC0MDLCmregister Set upC0MCONFm RTR bit Set upC0MIDlm and C0MIDHm register Clear the CINTS0 bits Read the C0TGPT register Clear the TOVF b...

Page 968: ...g transfer requests using this process 3 The user application can check the TSTAT bit periodically or it can check after the transmission is complete and interrupted 4 While transfer abort processing is in progress do not perform new transfer requests including in other packet buffers 5 When a transmission continues in the same packet cache or only one packet cache is used determining whether the ...

Page 969: ...by clearing the TRQ bit instead of the RDY bit 2 Before issuing a sleep mode transition request verify that no transfer requests use this processing 3 The user application can check the TSTAT bit periodically or it can check after the transmission is complete and interrupted 4 While transfer abort processing is in progress do not perform new transfer requests including in other packet buffers 5 Wh...

Page 970: ...any transfer requests when ABT transfer abort processing is in progress 2 After the ABTTRG bit is cleared after ABT mode is aborted a CAN sleep mode CAN stop mode conversion request is issued as shown in Figure 22 73or Figure 22 74 When clearing a transfer request in a zone other than the ABT zone follow the procedure shown in Figure 22 72 Clear the TRQ bit of the packet cache that is sent aborted...

Page 971: ...on with ABT Note 1 Do not set any transfer requests while ABT transfer abort processing is in progress 2 Issue a CAN sleep mode CAN stop mode request after ABTTRG is cleared stop in ABT mode following Figure 22 7322 73 Figure 22 74 When clearing a transfer request in an area other than the ABT area follow the procedure shown in Figure 22 72 Set the ABTCLR bit ABTTRG 0 no t yes Send abort Clear sen...

Page 972: ...ssage buffer and the receive history list register in case of a pending execution of sleep mode If MBON is detected to be cleared after setting MBON again the actions and results of the processing must be discarded before processing Before handling an RX interrupt it is recommended to cancel any sleep mode requests Read register C0LIPT Clear DN bits Read C0MDATAxm C0M0DLCm C0MIDLm andC0MIDHmregist...

Page 973: ...ck the MBON flags at the beginning and end of an interrupt in order to check access to the message buffer and the receive history list register in case of a pending execution of sleep mode If MBON is detected to be cleared after setting MBON again the actions and results of the processing must be discarded before processing Before handling the RX interrupt it is recommended to cancel any sleep mod...

Page 974: ...ed sleep pattern is executed If MBON is detected to be cleared then after setting MBON again the actions and results of the processing must be discarded before processing 2 If ROVF is set the receive history list is inconsistent Consider scanning all configured receive buffers for receive purgeCINTS1位 Read register C0RGPT Clear ROVF bit Clear DN bit Read C0MDATAx m C 0MDLCm C0MeDLm C 0MIDHmregiste...

Page 975: ...CAN sleep mode perform according to Figure 22 71or Figure 22 72 Set upPSMODE0 bit Set upPSMODE1 bit ThePMODE Access registers other than the C0CTRL and C0GMCTRL registers Settings C0CTRL SandtOPMODE purge CINTS5 bit Start PSMODE 1 0 00B PSMFROME0 1 no t yes CAN sleep mode no t PSMFROME1 1 yes Apply CAN Sleep Mode Again yes CAN stop mode no t end no t INITmode yes ...

Page 976: ...ode by user clear PSMODE0 bit end clear CINTS5 bit after explicit edge is detected when CAN clock is activated activate release CAN sleep mode via CAN Bus when CAN clock disabled activate release CAN sleep mode via CAN Bus detect explicit edge clear CINTS5 bit clear PSMODE0 bit Note CAN Clock Off With CPU standby mode the CAN module clock is turned off and the CAN module is in sleep mode ...

Page 977: ...g the bus shutdown recovery sequence all TRQ bits are cleared Note When a request is made to transition from initialization mode to any other mode of operation to perform the bus shutdown recovery sequence again in the bus shutdown recovery sequence the Receive Error counter is cleared Therefore it is necessary to detect the 11 consecutive recessive bits on the bus again 128 times Note OPMODE Norm...

Page 978: ... shutdown recovery sequence all TRQ bits are cleared Note When a request is made to transition from initialization mode to another mode of operation to perform the bus shutdown recovery sequence again in the bus shutdown recovery sequence the Receive Error counter is cleared Therefore it is necessary to detect the 11 consecutive recessive bits on the bus again 128 times Note OPMODE Normal operatio...

Page 979: ...Note Between setting the EFSD bit and clearing the GOM bit do not read or write any registers through the software Note that if an interrupt or DMA occurs it is not considered sequential access and the forced close request is invalid Clear Gather bits Begin INIT mode Closed successfully GOM 0 EFSD 0 end SetEFSD bit ClearGOM bit Begin no t GOM 0 yes Closed successfully GOM 0 EFSD 0 end ...

Page 980: ...1 02 Figure 22 84 Error handling Check the CAN module status read register C0INFO Clear CINTS2 bit Check the CAN protocol error status read register C0LEC clear CINTS3 bit Clear CINTS4 bit Begin The error is interrupted CINTS2 1 no t yes no t CINTS3 1 be CINTS4 1 no t be end ...

Page 981: ... to enter CPU standby mode check if CAN is in sleep mode When CAN sleep mode is detected until the CPU is set to standby mode CAN sleep mode may be canceled by the wake up of the CAN bus Set the PSMODE0 bit Clear PSMODE0 bits Clear ThereNTS5 bit Set the CPU standby mode Begin PSMODE0 1 no t yes CAN sleep mode no t no t MBONbit 0 yes CINTS5bit 1 yes end ...

Page 982: ...up Note THE CAN STOP MODE CAN ONLY BE RELEASED BY WRITING 01B TO THE PSMODE 1 0 BIT OF THE CNCTRL register and not by a change in the CAN bus state Clear PSMODE0 bits Clear ThereNTS5 bitNote Set the PSMODE0 bit Set the PSMODE1 bit Set the CPU standby mode Begin PSMODE0 1 no t yes CAN sleep mode no t PSMODE1 1 yes CAN stop mode no t MBONbit 0 yes end ...

Page 983: ...ed by a pin with different levels When the internal data bus accesses the LBDATA registers data transfer begins Supports 8 16 bit read and write operations The transmission speed can be controlled up to 10MHz through the following settings Select the input clock Set the transfer time Set the waiting status The following two events can trigger DMA DMA supports interrupt triggering Internal data tra...

Page 984: ...D0 Control pins DBWR DBRD Mode 80 IMD 0 R W E Mode 68 IMD 1 Data registers LCD bus interface data register LBDATA LBDATAL LCD bus interface read data registers LBDATAR LBDATARL Control registers LCD Bus Interface Mode Register LBCTL LCD bus interface cycle register LBCYC THE LCD BUS INTERFACE WAITS STATUS REGISTER LBWST Port mode control register PMCx Port mode register PMx Port register Px Regist...

Page 985: ...quence is as follows 15 8 70 Write register LBDATA Writing to the LBDATA register immediately sets the LBCTL BYF flag bit up If no LCD bus transfer is in progress at this time LBCTL TPF 0 the data is copied to the write cache and the LBCTL BYF flag bit is cleared to zero If a transfer is in progress at this time LBCTL TPF 1 the data is not copied to the write cache until the transfer is complete A...

Page 986: ...et occurs lbDATAR has a reset value of 0000H Figure 23 3 Format of the LCD bus interface read data registers LBDATAR LBDATARL Address 0x40045412H reset value 0000H R W LBDATARL Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBDATAR By reading this register the data transferred to the LBDATA register during the previous read operation can be obtained without having to start the LCD bus transfer again...

Page 987: ...t to enable or disable clocks to each peripheral hardware Reduce power consumption and noise by stopping clocking hardware that is not in use To use the LCD bus interface bit1 LCDBEN must be set to 1 The PER1 register is set via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 00H Figure23 4 Perimeter Enable Register PER3 Address 0x400208...

Page 988: ...During write access to the bus interface INTLCDB is generated as soon as data is moved from the LBDATA register to the write buffer During read access to the bus interface INTLCDB is generated as soon as the data in lbDATA and LBDATAR registers is available 1 An interrupt occurs when the DATA transmission of the LCD bus interface is complete TPF External bus interface transmission flags 0 The exte...

Page 989: ...is the clock period of the selected clock set by LBC1 and LBC0 2 LBCYC 2 23 3 4 The LCB bus interface waits for control registers LBWST LBWST is used to control the number of cycles in which the LCD bus interface waits for state The number of periods of wait state determines the duration of D B W R and DBRD signals This duration must be shorter than the cycle time LBWST is set using 8 bit memory m...

Page 990: ...he control registers for the multiplexed port function port mode register PMxx port register Pxx and port mode control register PMCxx must be set For details please refer to 2 3 1 Port Mode Register PMxx 2 3 2 Port Register Pxx and 2 3 6 Port Mode Control Registers PMCxx For details please refer to 2 5 Register Settings When Using the Multiplexing Function ...

Page 991: ...ming mode 80 In mode 80 D B W R is the optional communication number for the write action D B R D is the optional communication number for the read action Note 1 T is the clock cycle of the internal clock SPCLK configured by LBC1 and LBC0 bits 2 CYC is the number of clock cycles selected by LBCYC LBCYC 2 is required 3 WST is the number of wait state clock cycles selected by LBWST and requires LBWS...

Page 992: ...f the pins are automatically switched by the LCD module After the pin is configured as DB 7 0 the pin is in input mode Db 7 0 works in input mode while the bus interface is working during read access and continues to remain in input mode after read access is complete Db 7 0 works in output mode during the bus interface operation during write access which also continues to remain in output mode aft...

Page 993: ...t h e w r i t e b u f f e r LBCTL The BYF flag bit is then cleared and an INTLDB valid signal for one clock cycle is output Transmission on the LCD bus interface starts at 8 bits of data 0 The flag bit LBCTL TPF is placed indicating that a transmission is in progress 3 DMA triggered by INTLDB writes a second set of 16 bits of data to LBDATA By querying the busy flag bit LBCTL BYF the CPU can also ...

Page 994: ...LDB valid signal for one clock cycle is output Transmission on the LCD bus interface starts at 8 bits of data 0 The flag bit LBCTL TPF is placed indicating that a transmission is in progress 3 DMA triggered by INTLCDB writes a second set of 8 bits of da ta to LBDATA By querying the busy flag bit LBCTL BYF the CPU can also write this 8 bits of data Operating the internal bus to write lbDATA registe...

Page 995: ...ardware implementation a The order of the run 1 a virtual read of the LBDATA register initiates a 4 byte read from an external LCD controller Busy flag bit LBCTL BYF was immediately put up Transmitting flag bits LBCTL The TPF is placed on the rising edge of the clock The data read from LBDATA belongs to the previous transfer data and can be ignored 2 the busy flag bit LBCTL BYF is cleared when the...

Page 996: ...rom LBDATA belongs to the previous transfer data and can be ignored 2 the busy flag bit LBCTL BYF is cleared when data from the LCD bus interface is sampled into the LBDATA registers available The interrupt signal INTLCD outputs the effective level of one clock cycle 3 performs a new read of LBDATA before the last transfer completed no cycle time elapses The busy flag bit LBCTL BYF is immediately ...

Page 997: ...n example of a write access to the LCD bus followed by a read access and vice versa In 80 mode LBCTL IMD 0 8 bits transfer as an example In 68 mode LBCTL IMD 1 the timing is the same when the RD strobe is considered to be a low effective E signal LBCTL EL 1 Figure 23 13 80 Mode LBTCTL IMD 0 8 bit write read write timing LBWST 4 LBCYC 7 LBCTL TCIS 0 ...

Page 998: ...ata transfers To avoid this you must do the following Avoid writing LBDATAx registers simultaneously on the LCD bus transmission When a transfer is in progress in order to ensure that the LBDATAx registers are not written the LBCTL TCIS sets 1 to decide whether to write to the LBDATAx registers according to whether a bus interface interrupt is generated It is recommended to use DMA transfer to loa...

Page 999: ...1 The BAT32G179 can be used as a master chip to provide a clock for display to the slave chip LCD driver via the CLKBUZ0 pin System Configuration The system clock is 32MHz and the LCDB access period is 8MHz fCLK 4 68 80 mode CL is provided by CLKBUZ0 fCLK 2 11 15 6kHz Figure 23 14 Connection example 1 Mode80 BAT32G179 P140 CLKBUZ0 Mode80 P10 P11 P12 Mode68 BAT32G179 P10 P11 P12 P140 CLKBUZ0 Mode68...

Page 1000: ...P10 P 1 1 and P12 are used as A0 CS1 and CS2 which is just an example can also use other pins Example 2 The BAT32G179 can be used as a master chip to provide a clock for display to the slave chip LCD driver via the CLKBUZ0 pin System Configuration fCLK 6MHz PCF21119x68 mode The fOSC is provided by the CLKBUZ0 pin fCLK 16 375kHz Figure 23 15 Connection Example 2 P140 CLKBUZ0 Mode68 BAT32G179 P10 Ta...

Page 1001: ...operating procedure of the LCD bus transmission A detailed explanation of each step is explained in the following subsections The reference section number on the right Figure23 16 LCD bus transmission Start LCD BUS Function Setting CLKBUZ0 Output Setting LCD BUS Port Setting LCD BUS Transmission End Refer to 24 6 2 2 Refer to 24 6 2 3 Refer to 24 6 2 4 Refer to 24 6 2 6 ...

Page 1002: ...riod e g 2 Figure23 17 LCD Bus Function Setup Flow 68 mode Start Clock Enable LCDB control register LCDB bus cycle LCDB bus wait End LCDBEN 1 LBCTL 68H LBCYC 0EH LBWST 02H Clock enable of LCDB marco LCD access mode mode68 LCDB clock fCLK 4 INTLCDB When LCD transmission finished 14 cycle time 2 wait cycle 80 mode Start Clock Enable LCDB control register LCDB bus cycle LCDB bus wait End LCDBEN 1 LBC...

Page 1003: ...6 Set P140 as the output pin of CLKBUZ0 Figure 23 18 CLKBUZ0 clock setup flow Start Clock selection of CLKBUZ0 CKS0 04H CLKBUZ0 fMAIN 16 End When the system clock is high the appropriate CLKBUZ0 divideover needs to be set to meet PCF2119x fOSC 120 450khz or S1D15E00 fOSC Specification for 40khz TYP See the LCD driver data sheet for details ...

Page 1004: ... DBD0 to DBD7 the hardware automatically switches to the output mode and does not require the user to set it himself Set the pin register to set the PIN output latch for DBD0 to DBD7 multiplexing to 0 Figure 23 19 LCD bus pin setup flow 68 mode using PCF2119x Start Set port registers P1 0x01 End Set port mode control registers Set port mode registers R W P06 DBWR E P05 DBRDNote2 D0 to D7 P80 to P8...

Page 1005: ...0 to P87 A0 P10 0 for command 1 for data CS1 P11 CS2 P12 CS1 CS2 01 is active PMC1 0x00 P10 P12 digital mode PM0 0x9F PM8 0x00 PM1 0xF8 PM14 0xFE P05 and PC06 output mode P80 to P87 input mode Note1 P10 P12 output mode P140 CLKBUZ0 output mode Note 1 The P80 to P 87 must be set to input mode to act as an LCD bidirectional communication bus 2 Because DBRD and D B W R are all active low P05 And the ...

Page 1006: ...gure 23 20 DMA transfer setup flow Start Set INTLCDB trigger on DMAEN4 0x80 End Set DMABAR register Set DMA control data Enable DMA channel 39 DMABAR 0x2000000 0 DMACR39 0x0104 DMBLS39 0x1 DMACT39 1 DMRLD39 1 DMSAR39 0x20001000 DMDAR39 0x40045410 FIFO bit 1 source address fixed Transmission data size 1byte One trigger transmit one time RAM address as source address LBDATA address as destination ad...

Page 1007: ...splays all points on off Normal display mode 0x20001004 61H Duty cycle setting 2 byte Set the duty cycle to 1 8 and the starting point of the block to 0 COM0 to 3 0x20001005 00H 0x20001006 81H Electrical parameters 2 byte Set the electrical parameter register 05H small 0x20001007 05H 0x20001008 40H Temperature gradient settings Set the temperature gradient to 0 06 C 0x20001009 8AH Displays the sta...

Page 1008: ... flashing off 01H Clear the screen Determines the value 07H Portal mode setting Address plus 1 to show shifts Note Specify the same instruction to ensure that there is enough BF check time The LCD bus communication flow without DMA mode is as follows When fOSC 450kHz it takes about 330μs 165 driver oscillator cycles to complete the clean screen command and about 6μs 3 driver oscillator cycles for ...

Page 1009: ...that can be transmitted Address space Full address range space source Full address range space is optional target Full address range space is optional Maximum number of transfers Normal mode 65535 times Repeat pattern 65535 times The maximum transfer block size Normal mode 8 bit transmission 65535 bytes Normal mode 16 bit transmission 131070 bytes Normal mode 32 bit transmission 262140 bytes Repea...

Page 1010: ...o The CPU requests an interrupt that initiates the source and performs interrupt processing The transfer begins If the DMAENi0 DMAENi7 position of the DMAENi register is 1 boot allowed the transmission of data begins each time the DMA boot source occurs Transfer stops Normal mode Place DMAENi0 DMAENi7 at position 0 boot is prohibited When the DMACTj register changes from 1 to 0 at the end of the d...

Page 1011: ...2 Structure of the DMA A block diagram of the DMA is Figure 24 1241 Figure 24 1 diagram of DMA internal bus RAM control data vector table DMABAR DMAENi peripherial interrupt signal interrupt source transmit start source selection peripherial interrupt signal data transmission control ...

Page 1012: ...4 DMA base address register DMABAR The control data for the DMA is shown in Table 24 3 The control data for the DMA is allocated in the DMA control data area of the RAM The DMA control data area and the 704 byte region containing the DMA vector table area the starting address where the control data is saved are set up via the DMABAR register Table 24 3 DMA control data Register name symbol DMA con...

Page 1013: ...by the DMA Figure 24 2 memory image when the DMABAR register is set to 20000000H reserved Cortex M0 dedicated peripherial resource region reserved peripherial resource region reserved SRAM 32KB reserved data flash 2 5KB reserved main flash region 256KB FFFF_FFFFH E00F_FFFFH E000_0000H 4005_FFFFH 4000_0000H 2000_7FFFH 2000_0000H 0050_09FFH 0050_0000H 0003_FFFFH 0000_0000H DMAcontrol data region 640...

Page 1014: ...MABAR register and the low 10 bits are set separately by the vector table assigned by each boot source The distribution of control data is shown in Figure 24 3 Note 1 The DMAENi0 DMAENi7 bits of the corresponding DMAENi i 0 4 must be 0 No Boot when changing DMCRj DMBLSj DMACTj DMRLDj DMSARj Data from dmdaRj registers 2 DMACRj DMBLSj DMACTj DMRLDj DMSARj and DMSARj cannot be transmitted via DMA Acc...

Page 1015: ...BAT32G1x9 user manual Chapter 24 Enhanced DMA www mcu com cn 1015 1149 Rev 1 02 Table 24 4 controls the start address of the data Address Address Note baseaddr The setting value of the DMABAR register ...

Page 1016: ...i 0 4 register must be 0 Disable Startup when changing the start address of the DMA control data area set in the vector table Figure 24 4 control the start address and vector table of the data The case where the DMABAR register is set to 2000000H example control data 39 control data 3 control data 20 control data 2 control data 1 control data 0 20000040H 20000050H 20000060H 20000070H 20000180H 200...

Page 1017: ...ddress of the DMABAR register is 11H High speed SPI0 communication end note 18 The setting address of the DMABAR register is 12H Timer4 s channel 0 count or snap end 19 The setting address of the DMABAR register is 13H Timer4 s channel 1 count or snap end 20 The setting address of the DMABAR register is 14H Timer4 s channel 2 count or snap end 21 The setting address of the DMABAR register is 15H T...

Page 1018: ...ster is set via the 8 bit memory operation instruction After generating a reset signal the value of this register changes to 00H Figure 24 5 Peripheral enable the format of register 1 PER1 Address 0x4002081A after reset 00H R W symbol PER1 DMAEN Provides control of the input clock of the DMA 0 Stop providing the input clock DMA cannot run 1 An input clock is provided DMA can run 24 3 5 DMA control...

Page 1019: ... invalid CHNE Allow disable for chain transfers 0 Chain transfer is prohibited 1 Chain transfer is allowed The DMACR39 register must be placed at chne position 0 chain transfer is prohibited DAMOD Control of the delivery destination address 0 fixed 1 Increasing When the MODE bit is 1 repeat mode and the RPTSEL bit is 0 the transfer target is the repeating region the SETTING of the DAMOD bit is inv...

Page 1020: ... DMBLSj12 DMBLSj11 DMBLSj10 DMBLSj9 DMBLSj8 7 6 5 4 3 2 1 0 DMBLSj7 DMBLSj6 DMBLSj5 DMBLSj4 DMBLSj3 DMBLSj2 DMBLSj1 DMBLSj0 DMBLSj The size of the transfer block 8 bit transmission 16 bit transmission 32 bit transmission 00H Prohibit settings Prohibit settings Prohibit settings 01H 1 byte 2 bytes 4 bytes 02H 2 bytes 4 bytes 8 bytes 03H 3 bytes 6 bytes 12 bytes FDH 253 bytes 506 bytes 1012 bytes FE...

Page 1021: ...10 9 8 DMACTj DMACTj15 DMACTj14 DMACTj13 DMACTj12 DMACTj11 DMACTj10 DMACTj9 DMACTj8 7 6 5 4 3 2 1 0 DMACTj7 DMACTj6 DMACTj5 DMACTj4 DMACTj3 DMACTj2 DMACTj1 DMACTj0 Address Refer to 24 3 2Control data24 3 224 3 2Control data Control data allocation24 3 2Control data After reset indefinite value R W DMACTj Number of transfers 00H Prohibit settings 01H 1 time 02H 2 times 03H 3 times FDH 253 times FEH...

Page 1022: ...loaded into the DMACT register the setting value must be the same as the initial value of the DMACT register Figure 24 9 DMA transfer times reload register j DMRLDj Address Refer to 24 3 2Control data After reset indefinite value R W Symbol 15 14 13 12 11 10 9 8 DMRLDj DMRLDj15 DMRLDj14 DMRLDj13 DMRLDj12 DMRLDj11 DMRLDj10 DMRLDj9 DMRLDj8 7 6 5 4 3 2 1 0 DMRLDj7 DMRLDj6 DMRLDj5 DMRLDj4 DMRLDj3 DMRL...

Page 1023: ... 1 0 DMSARj7 DMSARj6 DMSARj5 DMSARj4 DMSARj3 DMSARj2 DMSARj1 DMSARj0 Note 1 Access to DMSARj registers cannot be made via DMA transfer 24 3 10 DMA destination address register j DMDARj j 0 39 This register specifies the destination address at which the data is transferred When the SZ bit of the DMACRj register is 01 16 bits transmitted the lowest bit is ignored and treated as a even address When t...

Page 1024: ...5003H DMAEN3 40005004H DMAEN4 after reset 00H R W symbol 7 6 5 4 3 2 1 0 DMAENi DMAENi7 DMAENi6 DMAENi5 DMAENi4 DMAENi3 DMAENi2 DMAENi1 DMAENi0 DMAENi7 DMA boot enable i7 0 Disable startup 1 Allow startup Depending on the condition under which the end of transmit interrupt occurs the DMAENi7 bit becomes 0 disables startup DMAENi6 DMA boot enable i6 0 Disable startup 1 Allow startup Depending on th...

Page 1025: ...or CSI00 or transfer end for buffer null IIC00 Transmit end received by UART0 Tran smit End for CSI01 or Transmit End for Buffer Null IIC01 End of A D conversion KEY input INTP7 DMAEN2 15 bit interval timer interrupt The end of the count or the end of the capture of channel 3 of the timer array unit 0 The end of the count or the end of capture for channel 2 of the timer array unit 0 The end of the...

Page 1026: ...5 DMSETi4 DMSETi3 DMSETi2 DMSETi1 DMSETi0 DMSETin The position register for DMAENin 0 No assertion is generated 1 Set the bit n of DMCENi to 1 Note i 0 4 n 0 7 24 3 13 DMAENi reset register DMCLRi This is the reset register that DMA initiates to allow register DMAENi and setting the corresponding bit to 1 resets the corresponding bit of DMAENi to 0 Figure 24 14 DMAENi reset register DMCLRi i 0 4 a...

Page 1027: ... DMA vector table areas please refer to 24 3 1DMA control data areas and DMA vector table areasareas Note 5 Set the register to keep 1024Byte aligned that is set the lower 10 bits to zero DMA hardware ignores low 10 bits 6 The register can only be accessed by WORD IGNORED and HALFWORD access Figure 24 15 DMA Base Address Register DMABAR Address 40005008H After reset 00000000H R W symbol 31 30 29 2...

Page 1028: ...en the data transmission in the case of chain transmission continuous initial transmission is set to the DMAENi0 DMAENi7 position of the corresponding DMAENi register in the DMA operation 0 disables startup In normal mode a DMACTj j 0 39 register is transferred to 0 In repeat mode the RPTINT bit of the DMACRj register is 1 interrupts are allowed and the DMACTj register becomes 0 Of The internal fl...

Page 1029: ... j DMBLSj The size of the data block to be transferred by 1 boot DMA transmit times register j DMACTj The number of times the data was transferred The number of DMA transfers reloads register j DMRLDj is not used Note DMA source address register j DMSARj The address of the source from which the data is transmitted DMA destination address register j DMDARj The address to which the data is transmitt...

Page 1030: ...tinuous A D conversion results DMABAR 20000000H vector address 2000000AH 0AH DMACR10 200000E0H 0048H DMBLS10 200000E2H 0001H DMACT10 200000E4H 0028H DMSAR10 200000E8H 40045004H DMDAR10 200000ECH 20000400H DMAEN1 04H start A D conversion A D conversion completion interrupt Yes DMACT10 01H No data transmit No generate A D conversion completion interrupt request DMAEN1 00H data transmit interrupt han...

Page 1031: ...0000H vector address 2000000CH 0CH DMACR12 20000100H 0004H DMBLS12 20000102H 0001H DMACT12 20000104H 0008H DMSAR12 20000108H 20000400H DMDAR12 2000010CH 40041310H DMAEN1 10H start A D conversion transmit buffer empty interrupt Yes DMACT12 01H No data transmit No generate A D transmit buffer empty interrupt DMAEN1 00H data transmit interrupt handling Yes UART0 transmit buffer RAM 20000400H 2000040F...

Page 1032: ...ister is generated DMAENi7 position 0 no boot When the RPTINT bit of the DMACRj register is 0 interrupt is prohibited even if the data transfer of the DMACTj register becomes 0 There is also no interrupt request and the DMAENi0 DMAENi7 bits do not change to 0 The repeating mode register function and data transfer are shown in Table 24 8and Figure 24 20 Table 24 8 Register functions for repeat mode...

Page 1033: ...0 0 1 fixed Duplicate areas SRC DST N X 1 0 1 Increasing Duplicate areas SRC N DST N X 0 or 1 DMACTj register 1 FFFFFFFFH DMBLSj register N DMACTj register 1 DMSARj register SRC DMDARj register DST j 0 39 00000000H Settings for the DMACR register Control of the source address Control of the destination address The source address after transmission The destination address after transmission DAMOD S...

Page 1034: ...o port register 1 40040301H Disable repeat mode interrupts Figure 24 21 repeat mode example 1 Using the stepper motor of the port to control the pulse output internal handling automatically executed by DMA DMABAR 20000000H vector address 200000013H 13H DMACR19 20000170H 0003H DMBLS19 20000172H 0008H DMACT19 20000174H 0008H DMSAR19 20000178H 2000H DMDAR19 2000017CH 40040301H DMAEN2 08H configure Ti...

Page 1035: ...om 1200H to 12FEH to the D A conversion value setting register 0 40044734H Disable repeat mode interrupts Figure 24 22 repeat mode example 2 Sine wave output using an 8 bit D A converter internal handling automatically executed by DMA DMABAR 20000000H vector address 200000013H 13H DMACR19 20000170H 0003H DMBLS19 20000172H 0001H DMACT19 20000174H 00FFH DMRLD19 20000176H 00FFH DMSAR19 20000178H 2000...

Page 1036: ...rol data setting is valid while the number of transmissions of control data processed later by the second is invalid The flowchart of the chain transfer is shown in Figure 24 23 Figure 24 23 chain transmission DMDAR2 register DMSAR2 register DMRLD2 register DMACT2 register DMBLS2 register DMACR2 register DMDAR1 register DMSAR1 register DMRLD1 register DMACT1 register DMBLS1 register DMACR1 registe...

Page 1037: ...ontinuous A D conversion results are used for UART0 transmission DMABAR 20000000H A D conversion result control data configuration vector address 2000000AH 0AH DMACR10 200000E0H 0058H DMBLS10 200000E2H 0001H DMACT10 200000E4H 0028H DMSAR10 200000E8H 40045004H DMDAR10 200000ECH 20000400H DMAEN1 04H start A D conversion A D conversion completion interrupt Yes DMACT10 01H No No generate A D conversio...

Page 1038: ...MRLDj DMSARj the data of the DMDARj register Must be 0 prohibited at the DMAENi0 DMAENi7 bits of the corresponding DMAENi i 0 4 register DMA Startup when you change the start address of the DMA control data area that is set in the vector table 24 5 2 The DMA controls the allocation of data areas and DMA vector table areas The regions where DMA control data and vector tables can be assigned vary de...

Page 1039: ...AMOD SAMOD RPTSEL MODE source target DMACTj register DMRLDj register DMSARj register DMDARj register 0 0 X 0 fixed fixed Write back Write back Do not write back Do not write back 1 0 1 X 0 Increa sing fixed Write back Write back Write back Do not write back 2 1 0 X 0 fixed Increa sing Write back Write back Do not write back Write back 2 1 1 X 0 Increa sing Increa sing Write back Write back Write b...

Page 1040: ...rce between entering the DMA boot source and ending the DMA transfer The DMA boot allow bit corresponding to that boot source cannot be manipulated at the location where the DMA boot source is generated If the DMA boot source sends a competition the CPU determines the priority when it accepts the DMA transfer and decides to start the boot source For the priority of the startup source refer to the ...

Page 1041: ...er RTC mode Deep sleep mode Can accept the DMA startup source and perform DMA transfer note 1 Note 1 In deep sleep mode DMA transmission can be performed after the DMA startup source is detected and the deep sleep mode can be returned after the transfer is completed However because the code flash and data flash stop running in deep sleep mode you cannot set flash as the transfer source ...

Page 1042: ...ng without going through the CPU and directly perform collaborative operation between peripheral functions EVENTC has the following features Depending on the product event signals for 23 peripheral functions can be linked directly to specified peripheral functions Depending on the product the event signal can be used as the starting source for the operation of 1 of the 10 peripheral functions 25 2...

Page 1043: ...arget selection register 07 ELSELR07 Event output target selection register 08 ELSELR08 Event output target selection register 09 ELSELR09 Event output target selection register 10 ELSELR10 Event output target selection register 11 ELSELR11 Event output target selection register 12 ELSELR12 Event output target selection register 13 ELSELR13 Event output target selection register 14 ELSELR14 Event ...

Page 1044: ...link target peripheral function when it accepts an event are shown in Table 25 3 Figure 25 2 Format of the event output target selection register n ELSELRn address 40043400H ELSELR00 40043416H ELSELR22 after reset 00H R W symbol 7 6 5 4 3 2 1 0 ELSELRn 0 0 0 0 ELSELn3 ELSELn2 ELSELn1 ELSELn0 ELSELn3 note 1 ELSELn2 ELSELn1 ELSELn0 Selection of event links 0 0 0 0 Disable event links 0 0 0 1 Select ...

Page 1045: ...ures A0 compares match A 0 INTTMM0 ELSELR09 The timer M input captures B0 compares match B 0 INTTMM0 ELSELR10 The timer M input captures A1 compares match A1 INTTMM1 ELSELR11 The timer M input captures B1 compares match B1 INTTMM1 ELSELR12 Timer M underflow TMM underflow signal ELSELR13 Timer A underflow end of pulse width measurement period end of pulse period measurement INTTMA ELSELR14 The time...

Page 1046: ... DA1 Note 3 Real time output Note 1 To select the timer input of Timer4 channel 0 as the link target peripheral function the operating clock of channel 0 must first be set to the operating clock of channel 0 through the timer clock selection register 0 TPS0 fCLK enable register 1 NFEN1 to set the noise filter at the TI00 pin as OFF TNFEN00 0 and the timer input used by channel 0 is set to the even...

Page 1047: ...elationship between interrupt handling and EVENTC is shown in Fig 25 3 This figure uses the relationship between an interrupt request status flag and a peripheral function of the interrupt allow bit which controls whether it is allowed or prohibited Peripheral functions that accept events through EVENTC operate according to the receiver peripheral functions after receiving the event see Table Tabl...

Page 1048: ...ces EventC events become the counting source for timer A directly 5 Timer B Input capture for TBIOB It is triggered from the time the EVENTC event has occurred after 2 or 3 fCLK cycles have elapsed 6 Timer M Input capture for TMIOD0 It is triggered after the event of an EVENTC event passes through the operating clock cycles of 2 or 3 timers M Forced cutoff of the pulse output It becomes a forced c...

Page 1049: ...rocessor has built in NVIC functions please refer to the Cortex M0 processor user manual 26 1 The types of interrupt function There are two types of interrupt functions 1 Interrupts can be masked This is an interrupt that is subject to masking control If the interrupt mask flag register is not open the interrupt request will not be responded to even if it is generated It can generate a standby rel...

Page 1050: ...ed by UART2 has occurred 10 INTST0 INT SSPI00 INTII C00 The end of the transmission sent by the UART0 or the transfer end of the buffer null interrupt SSPI00 or the transfer end of the buffer null interrupt IIC00 11 INTSR0 INT SSPI01 INTI IC01 Transmit end received by UART0 Transmit end of SSPI01 or Transmit end of buffer null interrupt IIC01 12 INTSRE0 A communication error received by UART0 has ...

Page 1051: ...1 29 INTTMB Timer B s input capture comparison matching overflow and underflow interrupts 30 INTTMC Overflow of timer C 31 INTFL Flash programming is over 32 INTOSDC The stop vibration detection is interrupted 33 INTP6 Detection of pin input edges exterior B 34 INTP7 Detection of pin input edges 35 INTP8 Detection of pin input edges 36 INTP9 Detection of pin input edges 37 INTP10 Detection of pin ...

Page 1052: ...with a high 8 bit timer 48 INTDIV The divider calculation ends Note 1 The basic composition types A to D correspond to A Figure 26 1D of FIG 261 respectively 2 The high speed SPICHS0 module is proprietary to the BAT32G179 product so the interrupt source 42 is reserved when the BAT32G139 product is used ...

Page 1053: ...TC1TRX CAN1 send ends 64 INTOCRV High speed internal oscillation self adjustment ends 65 reserved 66 reserved 67 reserved 68 reserved 69 reserved 70 reserved 71 reserved 72 reserved 73 reserved 74 INTSPI1 High speed SPICHS1 transmission ends interrupt Note 2 interi or A 75 reserved 76 INTLCDB The LCD bus transfer ends with an interrupt interi or A 77 reserved 78 reserved 79 reserved 80 INTIICA1 II...

Page 1054: ...terior A 91 reserved 92 reserved 93 INTC2REC CAN2 receives the end note 3 interior A 94 INTC2WUP CAN2 wake up note 3 95 INTC2TRX CAN2 sends the end note 3 Not Maskable INTWDT Watchdog timer interval interrupt note 2 interior D Note 1 The basic composition types A to D correspond to A Figure 26 1D of FIG 261 respectively 2 This is the case where the bit7 WDTINT of the option byte 000C0H is set to 1...

Page 1055: ... 1 basic structure of the interrupt function A Internally maskable interrupts B Externally maskable interrupts INTPn note 0 n 11 Internal bus MK IF Standby dismiss signal CPU IRQ Internal bus MK IF Standby dismiss signal CPU IRQ External break edges Allow registers EGN EGP edge Detection circuit ...

Page 1056: ... Interrupts cannot be masked Note Unmasked interrupt request flagIF does not have a physical register and cannot generate an interrupt request by reading or writing registers on the bus Internal bus MK IF Standby dismiss signal CPU IRQ Key back Mode registers KRM Key break Detection circuit CPU NMI Internal bus Standby dismiss signal IF ...

Page 1057: ...028H IF11 4000602CH IF12 40006030H IF13 40006034H IF14 40006038H IF15 4000603CH IF16 40006040H IF17 40006044H IF18 40006048H IF19 4000604CH IF20 40006050H IF21 40006054H IF22 40006058H IF23 4000605CH IF24 40006060H IF25 40006064H IF26 40006068H IF27 4000606CH IF28 40006070H IF29 40006074H IF30 40006078H IF31 4000607CH Reset value 0000_0000HR W 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 ...

Page 1058: ...06144H MK18 40006148H MK19 4000614CH MK20 40006150H MK21 40006154H MK22 40006158H MK23 4000615CH MK24 40006160H MK25 40006164H MK26 40006168H MK27 4000616CH MK28 40006170H MK29 40006174H MK30 40006178H MK31 4000617CH Reset value FFFF_FFFFHR W 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 MKmT Reserved MKT 15 14 13 12 11 10 9 8 MKmH Reserved MKH 7 6 5 4 3 2 1 0 MKmL Reserved MKL MKmL Int...

Page 1059: ...01 INTII C01 IF11 IFL MK11 MKL 43 reserved IF11 IFH MK11 MKH 12 INTSRE0 IF12 IFL MK12 MKL 44 INTTM01H IF12 IFH MK12 MKH 13 INTST1 INT SSPI10 INTII C10 IF13 IFL MK13 MKL 45 reserved IF13 IFH MK13 MKH 14 INTSR1 INT SSPI11 INTII C11 IF14 IFL MK14 MKL 46 reserved IF14 IFH MK14 MKH 15 INTSRE1 IF15 IFL MK15 MKL 47 INTTM03H IF15 IFH MK15 MKH 16 INTIICA0 IF16 IFL MK16 MKL 48 INTDIV IF16 IFH MK16 MKH 17 IN...

Page 1060: ...eserved IF11 IFT MK11 MKT 76 reserved IF12 IFT MK12 MKT 77 reserved IF13 IFT MK13 MKT 78 reserved IF14 IFT MK14 MKT 79 reserved IF15 IFT MK15 MKT 80 INTIICA1 IF16 IFT MK16 MKT 81 INTTM14 IF17 IFT MK17 MKT 82 INTTM15 IF18 IFT MK18 MKT 83 INTTM16 IF19 IFT MK19 MKT 84 INTTM17 IF20 IFT MK20 MKT 85 reserved IF21 IFT MK21 MKT 86 reserved IF22 IFT MK22 MKT 87 reserved IF23 IFT MK23 MKT 88 reserved IF24 I...

Page 1061: ...BAT32G1x9 user manual Chapter 26 Interrupt function www mcu com cn 1061 1149 Rev 1 02 Figure 26 4 Flag registers and CPU IRQ relationship Internal bus IFnL MKnL MKnH IFnH Internal bus CPU IRQn IFnT MKnT ...

Page 1062: ...GP1 and the enable registers for the falling edge of the external interrupt EGN0 EGN1 Address 40045B38H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP0 Address 40045B39H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN0 Address 40045B3AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP1 Address 40045B3BH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN1 EGPn EGNn Effective edge selection for the INTPn p...

Page 1063: ...EGN3 INTP3 EGP4 EGN4 INTP4 EGP5 EGN5 INTP5 EGP6 EGN6 INTP6 EGP7 EGN7 INTP7 EGP8 EGN8 INTP8 EGP9 EGN9 INTP9 EGP10 EGN10 INTP10 EGP11 EGN11 INTP11 NoteIf you switch the input port used by the external interrupt function to output mode an INTPn interrupt may be detected and an INTPn interrupt may be detected When switching to output mode the port mode register PMxx must be set to 0 after disabling th...

Page 1064: ...ate that can accept the maskable interrupt request and the interrupt request can be passed to the NVIC From the interrupt request flag set to 1 to the CPU s IRQ set to 1 only 1 clock is required BASECK INTAS IF MK IRQ 26 4 2 Acceptance of unaskable interrupt requests If an unscealable interrupt request is generated the interrupt request flag will be placed 1 and passed directly to the NVIC From th...

Page 1065: ...ey interrupt input pin KR0 to KR7 the input falling edge Table 27 1 key interrupt detection pin assignments Key interrupt pin Key return mode register KRM KR0 KRM0 KR1 KRM1 KR2 KRM2 KR3 KRM3 KR4 KRM4 KR5 KRM5 KR6 KRM6 KR7 KRM7 27 2 The structure of the key interrupt Key interrupts are made up of the following hardware Table 27 2 Structure of key interrupts item Control registers Control registers ...

Page 1066: ...nual Chapter 27 Key interrupt function www mcu com cn 1066 1149 Rev 1 02 Figure 27 1 Block diagram of key interrupt KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 Key return mode register INTKR ...

Page 1067: ... KRM6 KRM5 KRM4 KRM3 KRM2 K RM1 KRM0 KRMn Key interrupt mode control 0 Key interrupt signal is not detected 1 Detects a key interrupt signal Note 1 An internal pull up resistor can be used by using the object position 1 of the pull up resistor register PUx of the input pin by interrupting the key 2 If the object position bit of the KRM register is entered low on the input pin of the key interrupt ...

Page 1068: ...espectively The bits are placed 1 respectively In this case the output latch of Pxx can be 0 or 1 The PM x register is set via the 8 bit memory operation instruction After the reset signal is generated the value of this register changes to FFH An internal pull up resistor can be used in bits by a pull up resistor select register PU x For the format of the port mode register see 2 3 1 Port Mode Reg...

Page 1069: ...ttent operations can also be performed However in the case of the X1 clock because the wait time to ensure oscillation stability is required when decommissioning the deep sleep mode it is necessary to select the sleep mode if you need to start processing immediately through the interrupt request In either mode registers flags and data memory are all left set to before standby mode and the output l...

Page 1070: ...hey were in before they entered sleep mode The status of peripheral modules vibrators etc in sleep mode is shown in Table 28 1 Sleep mode can be set regardless of whether the CPU clock before setup is a high speed system clock a high speed internal oscillator clock or a sub system clock Note When the interrupt mask flag is 0 allow interrupt processing and the interrupt request flag is 1 generating...

Page 1071: ...nal oscillation device clock fII Bit0 WDSTBYON and bit4 WDTON via option bytes 000C0H and subsystem clocks Programmed for the WUTMMCK0 bit of the Mode Control Register OSMC WUTMMCK0 1 Oscillation WUTMMCK0 0 and WDTON 0 Stop WUTMMCK0 0 WDTON 1 and WDSTBYON 1 Oscillation WUTMMCK0 0 WDTON 1 and WDSTBYON 0 Stop CPU Stop running Code flash RAM Stop running can run when DMA is executed Port latch Remain...

Page 1072: ... RAM parity function It can be run when the DMA is performed SFR protection function Note Stop Running Automatically stops running when you move to sleep mode Disable Run Stops running before moving to sleep mode fIH High Speed Internal Oscillator Clock fIL Low Speed Internal Oscillator Clock fX X1 Clock fEX External master system time fXT XT1 Clock fEXS External Subsystem ...

Page 1073: ...s prohibited Real time clock RTC Can run 15 bit interval timer Watchdog timer Refer to Chapter 14 Watchdog Timer Timer A When RTCLPC 0 it can run otherwise it is prohibited Timer M Timer B Timer C Clock output buzzer output A D converter Disables operation D A converter When RTCLPC 0 it can run otherwise it is prohibited Comparator Can run Universal Serial Communication Unit SCI When RTCLPC 0 it c...

Page 1074: ...the procedure is executed after the transfer to the reset vector address Figure 28 2Relieves sleep mode by resetting CPU status normal operation sleep mode reset signal reset period reset process note1 normal operation Note 1 For the reset processing time please refer to Chapter 28 Reset Function For reset processing time for power on reset POR circuits and voltage detection LVD circuits refer to ...

Page 1075: ... interval timer Watchdog timer Refer to Chapter 14 Watchdog Timer Timer A Can be run in event counting mode without TAIO input filter selected Can run when the subsystem clock is selected as the counting source and the RTCLPC bit of the OSMC register is 0 Operates when a low speed internal oscillator is selected as the counting source Outside of the above Operation is prohibited Timer M Disables o...

Page 1076: ...tion SFR protection function Note 1 Stop Running Automatically stops running when you move to deep sleep mode Disable Run Stops running before moving to deep sleep mode fIH High speed internal oscillator clock fII Low speed internal oscillator clock fX X1 clock fEX External master system clock fXT XT1 clock fEXS External subsystem clock ...

Page 1077: ...eep state depreparation time When the CPU clock is a high speed internal oscillation clock or an external clock input before entering deep sleep mode at least 20us When entering deep sleep mode before the CPU clock is a high speed system clock X1 oscillation At least 20us and a longer time in the oscillation settling time set by OSTS Additional LOCKUP time is required when the CPU clock is PLL clo...

Page 1078: ...e is executed after the transfer to the reset vector address Figure 28 4 Exit from sleep mode by resetting CPU status normal operation deep sleep state reset signal reset period reset process note1 normal operation Note For reset processing time please refer to Chapter 28 Reset Function For reset processing time for power on reset POR circuits and voltage detection LVD circuits refer to Chapter 29...

Page 1079: ...out of control or the voltage of the POR circuit and the LVD circuit is detected or the system reset request bit is set or the RAM parity test error occurs or the illegal memory is accessed Alternatively when a damping is detected a reset is generated and each hardware becomes in a state shown in Table 28 1 Note 1 When performing an external reset a low of 10us must be input to the RESETB pin If a...

Page 1080: ...erated by setting system reset request bit reset signal generated by RAM parity check error reset signal generated by illegal access registers RESF register read signal RESETB reset signal reset signal of power on reset circuit reset signal of voltage detection circuit reset reset reset reset reset erase eraseerase erase erase Note that an internal reset of the LVD circuit does not reset the LVD c...

Page 1081: ...tus RESETB pin internal reset signal normal operation reset period wait till osc precision stablized start X1 oscilation via software configuration normal operation high speed internal osc clock delay reset processing time while releasing external reset Port in except P130 Hi Z Note3 Note2 Note1 Port in P130 For resets caused by overflow of watchdog timers assertion of system reset request bits de...

Page 1082: ...st be set to high via software 2 Reset processing time when removing external reset 1st time after POR released 0 672ms TYP 0 832ms MAX in the case of LVD 0 399ms TYP 0 519ms MAX In the case of not using LVD 2nd time after the POR released 0 531ms TYP 0 675ms MAX in the case of LVD 0 259ms TYP 0 362ms MAX when LVD is not used When the supply voltage rises a voltage stabilization wait time of 0 99m...

Page 1083: ...running Watchdog timer Clock output buzzer output A D converter D A converter Note 1 Comparator Note 1 Universal Serial Communication Unit SCI Serial Interface IICA aFCAN Data Transfer Controller DMA Power on reset function Can perform inspection operations Voltage detection function It can be operated when the LVD is reset During other resets the operation stops External interrupts Stop running K...

Page 1084: ...ed or the RESF register was cleared 1 Generates an internal reset request CLMRF Internal reset request generated by the damping detection function 0 No internal reset request was generated or the RESF register was cleared 1 Generates an internal reset request RPERF internal reset request generated by a RAM parity error 0 No internal reset request was generated or the RESF register was cleared 1 Ge...

Page 1085: ...nput Reset of POR generated System reset requests a reset resulting from a position bit WDT generated reset Reset due to vibration stop detection Reset due to RAM parity errors Access to the reset generated by illegal memory LVD generated reset SYSRF Clear 0 Clear 0 Set 1 keep keep keep keep keep WDTRF keep Set 1 CLMRF keep Set 1 RPERF keep Set 1 IAWRF keep Set 1 LVIRF keep Set 1 The confirmation ...

Page 1086: ...l reset request due to watchdog Timer No Yes RPERF of RESF register 1 generate internal reset request due to RAM parity check error No Yes IAWRF of RESF register 1 generate internal reset request due to illegal accesss registers No Yes LVIRF of RESF register 1 generate internal reset request due to voltage detection circuit No Yes No generate power on reset external reset read RESF register save R...

Page 1087: ...sleep mode voltage detection circuitry or external reset When restarting operation you must confirm that the supply voltage has returned to the operating voltage range Note When the power on reset circuit generates an internal reset signal the reset control flag register RESF is cleared to 00H Note 1 The BAT32G1x9 includes several hardware that generates an internal reset signal When an internal r...

Page 1088: ...k diagram of the power on reset circuit is shown in Figure 29 1 Fig 29 1 Block diagram of the power on reset circuit basic voltage source VDD VDD internal reset signal 30 3 Operation of the power on reset circuit The timing of the generation of internal reset signals in the power on reset circuit and the voltage detection circuit is as follows ...

Page 1089: ...C of the oscillation settling time counter In the case of using the XT1 clock it is necessary to switch after confirming the oscillation stabilization time using the timer function etc 3 The time until the start of normal operation except for reaching VPOR 1 51V TYP After the voltage stabilization wait time the following is required after setting the RESETB signal high 1 Reset processing time when...

Page 1090: ...tch the CPU clock from a high speed internal oscillator clock to a high speed system clock or a sub system clock In the case of an X1 clock the oscillation settling time must be switched after the oscillation settling time is confirmed by the state register OSTC of the oscillation settling time counter In the case of using the XT1 clock it is necessary to switch after confirming the oscillation st...

Page 1091: ... from a high speed internal oscillator clock to a high speed system clock or a sub system clock In the case of an X1 clock the oscillation settling time must be switched after the oscillation settling time is confirmed by the state register OSTC of the oscillation settling time counter In the case of using the XT1 clock it is necessary to switch after confirming the oscillation stabilization time ...

Page 1092: ...errupt and a low voltage sense level VLVDL is used to generate a reset b Reset mode LVIMDS1 LVIMDS0 1 1 of the option bytes Use the 1 sense voltage VLVD selected by option byte 000C1H to generate or de reset c Interrupt mode LVIMDS1 LVIMDS0 0 1 of the options Use the 1 sense voltage VLVD selected by option byte 000C1H to generate an interrupt or de reset In each mode the following interrupt signal...

Page 1093: ...re 31 1 Figure 31 1 diagram of the voltage detection circuit internal bus voltage detection register LVIM LVIF LVIOMSK LVISEN voltage detection voltage level regsiter LVIM LVIMD LVILV reference voltage source internal reset signal INTLVI voltage detection voltage selection circuit N ch VDD VLVDH VLVDL VLVD LVIS1 LVIS0 of option byte 00C1H VPOC2 VPOC1 VPOC0 of option byte 00C1H VDD control circuit ...

Page 1094: ...ng is valid LVIOMSK Mask status flag for LVD output 0 LvD output masking is invalid 1 LVD output mask valid note 4 LVIF Voltage detection flag 0 The supply voltage VDD sense voltage VLVD or LVD is OFF 1 Supply voltage VDD detect voltage VLVD Note 1 The reset value varies depending on the reset source When the LVD is reset the value of the LVIM register is not reset and the original value is mainta...

Page 1095: ...tion bytes When an LVD reset occurs this register is not cleared to 00H When a reset other than LVD occurs the values of this register are as follows Option bytes for LVIMDS1 LVIMDS0 1 0 00H Option bytes for LVIMDS1 LVIMDS0 1 1 81H Option bytes for LVIMDS1 LVIMDS0 0 1 01H 2 Write 0 only if interrupt reset mode is selected LVIMDS1 bit and LVIMDS0 bits for option bytes are 1 and 0 respectively In ot...

Page 1096: ... 86V 2 75V 1 1 1 0 3 02V 2 96V 0 1 4 06V 3 98V 0 0 Setting values other than those described above is prohibited LVD settings reset mode Detect voltage The setting value of the option byte VLVD VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode settings rise falling LVIMDS1 LVIMDS0 1 67V 1 63V 0 0 0 1 1 1 1 1 77V 1 73V 0 0 1 0 1 88V 1 84V 0 1 1 1 1 98V 1 94V 0 1 1 0 2 09V 2 04V 0 1 0 1 2 50V 2 45V 1 0 1 1 2 61V 2...

Page 1097: ...f pins Note 1 You must write 1 to bit4 2 When the power supply voltage rises the reset state must be maintained through the voltage detection circuit or external reset before the power supply voltage reaches the working voltage range shown in the AC characteristics of the data sheet When the supply voltage drops it must be reset by transferring in deep sleep mode voltage detection circuitry or ext...

Page 1098: ...l Register LVIS Set the initial value of the Voltage Sense Level Register LVIS to 81H bit7 LVIMD is 1 reset mode bit0 LVILV is 1 voltage sense level VLVD Operation of LVD reset mode When power is turned on the reset mode LVIMDS1 LVIMDS0 1 1 exceeds the voltage sense level VLVD at the supply voltage VDD before maintaining the internal reset state of the LVD If the supply voltage VDD exceeds the vol...

Page 1099: ...n bytes low limit of working voltage range VPOR 1 51V TYP VPDR 1 50V TYP power supply voltage VDD internal reset signal VLVD Time POR reset signal LVD reset signal LVIRF flag RESF register LVILV flag LVIMD flag LVIF flag H H not cleared not cleared clear clear clear via software Note VPOR The POR supply voltage rises to the detection voltage VPDR POR supply voltage drop sense voltage ...

Page 1100: ...terrupt mode LVIMDS1 LVIMDS0 0 1 exceeds the voltage sense level VLVD at the supply voltage VDD before maintaining the internal reset state of the LVD If the supply voltage VDD exceeds the voltage sense level VLVD the internal reset of the LVD is released After removing the internal reset of lvd if the supply voltage VDD exceeds the voltage sense level VLVD an interrupt request signal for LVD is g...

Page 1101: ... via software LVIIF flag INTLVI LVIMK logo mask interrupt set by software Note2 Note2 Note1 Note 1 After generating a reset signal the LVIMK flag changes to 1 2 When the working voltage drops it must be reset by the transfer of deep sleep mode or external reset before the working voltage is lower than the working voltage range shown in the AC characteristics of the data sheet When restarting opera...

Page 1102: ...f the supply voltage VDD exceeds the high voltage sense level VLVDH the internal reset is dismissed When the operating voltage drops if the supply voltage VDD falls below the high voltage sense level VLVDH an interrupt request signal INTLVI of the LVD is generated and can perform arbitrary stack processing Thereafter if the supply voltage VDD is below the low voltage sense level VLVDL which result...

Page 1103: ...ar via software clear via software normal operation push stack operation wait for stablization via software 400us or 5 clock cycles fIL note 3 operation status LVIF flag LVISEN flag via software configuration LVIOMSK flag LVIMD flag LVILV flag LVIRF flag internal reset signal POR reset signal LVD reset signal INTLVI LVIIF flag Time Clear Clear clear via software note 2 clear via software note 3 pu...

Page 1104: ...t must be set according to the Setting Steps for Confirmation Reset of the Working Voltage of Figure 30 7 after the interruption occurs 3 When using the In progress reset mode it must be set according to the Figure 30 8 Initial Setup Steps for Interrupt Reset Mode after the reset is lifted Note VPOR The POR supply voltage rises to the detection voltage VPDR POR supply voltage drop sense voltage ...

Page 1105: ...ag LVIMD flag LVILV flag LVIRF flag internal reset signal POR reset signal LVD reset signal INTLVI LVIIF flag Time after release mask while VDD VLVDH due to LVIMD 1 reset mode the reset will be generated reset normal operation reset normal operation reset LVISEN flag via software configuration clear via software note 2 operation status clear via software wait for stablization via software 400us or...

Page 1106: ...R POR supply voltage drop sense voltage Figure 30 7 The setup steps for confirming resetting the operating voltage set LVILV bit to 0 configure high voltage detection voltage level VLVDH INTLVI occurs push stack operation LVISEN 1 LVILV 0 LVISEN 0 LVIOMSK 0 LVD reset occurs LVISEN 1 LVIMD 0 LVISEN 0 normal operation generate LVD internal reset Yes No No perform necessary push stack operation set L...

Page 1107: ...1 must be used to shield the reset or interrupt generated by the LVD The initial setup steps for interrupt reset mode are shown in Figure 30 8 Figure 30 8 Initial setup steps for interrupt reset mode power supply voltage arise confirm reset source LVIRF 1 LVISEN 1 wait time of voltage detection stablization Yes No refer to diagram 28 5 reset source confirmation steps set LVISEN bit to 1 mask volta...

Page 1108: ...he port etc must be made after waiting for different supply voltage fluctuation times in each system by using the software counter of the timer Fig 30 9 Example of software processing when the supply voltage fluctuation near the LVD detection voltage does not exceed 50ms reset initialization after 50ms configure TIMER4 measure 50ms clear WDT Yes No refer to diagram 28 5 reset source confirmation s...

Page 1109: ... performing an external reset a low of 10us must be input to the RESETB pin If an external reset occurs while the supply voltage rises the power must be switched on after inputting a low level to the RESETB pin and keeping it at least 10us low over the operating voltage range shown in the AC characteristics of the data sheet and then entering the high level 4 About the case when the operating volt...

Page 1110: ... flash area at high speed Generic CRC In CPU operation it is not limited to the code flash memory area but can be used for multi purpose inspection 2 RAM parity error detection When reading RAM data parity errors are detected 3 SFR protection function Prevents rewriting the SFR due to CPU loss of control 4 Frequency detection function Self test of CPU peripheral hardware clock frequency can be per...

Page 1111: ...A D test function Port Mode Select Register PMS Digital output signal level detection function on input output pins The contents of each register are described in 32 3 Operation of security features 32 3 Operation of security features 32 3 1 Flash CRC operation function high speed CRC The IEC60730 standard requires confirmation of data in flash memory and recommends CRC as a means of confirmation ...

Page 1112: ...he value of this register changes to 00H Figure 32 1 Format of the flash CRC control register CRC0CTL Address 40021810H reset 00H R W Symbol 7 6 5 4 3 2 1 0 CRC0CTL CRC0EN Operational control of high speed CRC operators 0 Stop running 1 Start the operation by executing the HALT instruction high speed CRC calculation range Note The expected value of the CRC operation result for comparison must be s...

Page 1113: ...uction After generating a reset signal the value of this register changes to 0000H Figure 32 2 Flash CRC Operation Result Register PGCRCL Address symbol after reset PGCRC15 0 The result of the operation of the high speed CRC 0000H FFFFH Saves the calculation results of the high speed CRC Note that the PGCRCL register can only be written if the CRC0EN bit7 of the CRC0CTL register bit is 1 The flowc...

Page 1114: ...ion value of CRC same difference abnormal compeltion configure CRC calculation range allows CRC calculation perform initialization of CRC calculation result register start CRC calculation via WFE instruction disable CRC calculation read CRC calculation result save expected value of CRC calculation result to last 4 bytes ahead of time compare with the pre stored expectation value Note 1 Objects tha...

Page 1115: ...LSB it is as follows as 78H 56H 34H etc The order of 12H is written to the CRCN register and the value of 08F6H is obtained from the CRCRD register This is the result of a CRC operation on the following bit order after the bit order of the data 12345678H is reversed CRCIN configure data bit representation of data reversed bit representation use polynomial to calculate obtained result reversed bit ...

Page 1116: ...W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRCD Note 1 To read the write value of a CRCD register the CRCRD register must be read before writing the CRCAN register 2 If the write operation of the CRCD register competes with the saving of the operation result the write operation is ignored operation process Figure 32 6 Flowchart of the CRC operation function Universal CRC Start save start and e...

Page 1117: ...ting data and check parity bits when reading data Therefore to allow ram parity error reset RPERDIS 0 to be generated the RAM region used must be initialized when the data is accessed and before reading the data Because it is running on a pipeline the CPU performs a read ahead and a RAM parity error may occur due to the uninitialized RAM area before reading the RAM area used Therefore to allow for...

Page 1118: ...y check parity check error occurs internal reset occurs normal operation enable reset due to parity check error RAM error handling confirm parity check error occurs disable reset due to parity check error Read RAM RAM parity check PRERF 1Note Note For confirmation of internal reset of RAM parity errors please refer to Chapter 28 Reset Function ...

Page 1119: ... of registers 0 Void A control register capable of reading and writing comparator functions 1 Effective The control register for the port function is invalid and can be read Protected SFR COMPPMDR COMPFIR COMPOCR CVRCTL CxRVM PGAxCTL PGASHMD CMPSELx GPORT Port function for control register protection 0 Void A control register capable of reading and writing port functions 1 Effective The control re...

Page 1120: ...IH High speed system clock fMX 2 Channel 1 input of Timer4 Timer input TI01 for channel 1 Low speed internal oscillator clock fIL 15kHz TYP Sub System Clock fSUB Note Figure 32 10 frequency detection function Univeral Timer Unit 0 Timer 40 channel 1 watchdog Timer WDT low speed internal osc clock 15Khz TYP secondary system clock fsub high speed system clock fMX high speed internal osc clock fIH fC...

Page 1121: ...ed as the A D conversion object ADTES1 ADTES0 0 0 through the ADTES register A D conversion of the ANIx pins conversion result 1 2 The positive reference voltage of the A D converter is selected by the ADTES register as the A D conversion object ADTES1 ADTES0 1 1 A D conversion of the positive reference voltage of the A D converter conversion result 2 2 The ANIx pin is selected as the A D conversi...

Page 1122: ... 1 02 Figure 32 11 Structure of the A D test function ADISS ADS4 0 ANI0 VREFPE ANI1 VREFNE ANIxx ANIxx temperature sensor internal reference voltage 1 45V VDD VSS ADREFM ADREFP ADTES1 0 A D convertor A D convertor Positive reference voltage A D convertor Negative reference voltage ...

Page 1123: ...ollowing settings are made When measuring the zero scale select the negative reference voltage as the A D conversion object When measuring full scale select a positive reference voltage as the A D conversion object For a register description refer to 15 2 10 32 3 6 2 Analog input channel specified register ADS This register specifies the input channel for the analog voltage converted from A D To m...

Page 1124: ...d pin when the pin is output mode the PMmn bit of the port mode register PMm is 0 Set the PMS registers via the 8 bit memory operation instructions After generating a reset signal the value of this register changes to 00H Figure 32 12 format of port mode selection register PMS Address 4004087BH after reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMS PMS0 Selection of data to read when the pin is in output ...

Page 1125: ...of the code in the flash memory Used to activate a bootstrap process with a safety mechanism The reference number provided by the 128 bit product unique identifier is unique to any BAT32 microcontroller in any case Under any circumstances the user cannot modify this identity Base address 0x0050_0E4C Address offset 0x00 Read only whose values are written at the factory Address offset 0x04 Read only...

Page 1126: ...ram of a temperature sensor Figure33 1Temperature Sensor Block Diagram 33 2 Registers for temperature sensors 33 2 1 Temperature sensor calibration data register TSN25 Address 0x500C6C symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After reset R W TSN25 TSN25 11 0 R Read only registers for recording calibration data for temperature sensors1 are automatically loaded when powered on or reset is initia...

Page 1127: ...1 V T2 Temperature measured experimentally at the second point C V2 Voltage output when the temperature sensor measures T2 V Slope The temperature slope of the temperature sensor V C slope V2 V1 T2 T1 Different sensors have different characteristics so we recommend measuring the following two different sample temperatures 1 Use an A D converter to measure the voltage V1 output of the temperature s...

Page 1128: ...sing these two sets of values the temperature slope can be calculated slope V2 V1 85 25 V1 3 0 CAL25 4096 V V2 3 0 CAL125 4096 V Using the above results the temperature can be calculated according to the following formula T Vs V1 slope 25 C T Measured temperature C Vs Output voltage V of the temperature sensor at T temperature obtained using the A D converter Method 2 If you use the temperature sl...

Page 1129: ...ate it through this value and the A D conversion result of the current VBG The voltage value of VDD 33 4 1 VDD calibration data register VDDCDR Address 0x500C64 symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After reset R W VDDCDR VDDCDR 11 0 R Read only register for recording VDD 3 The A D conversion result of VBG at 0v is automatically loaded when power is turned on or reset is started and each ch...

Page 1130: ... of the counter in sleep deep sleep mode The setting of the overflow timer of the watchdog The setting during which the watchdog timer window is opened The setting of the interval interrupt of the watchdog timer Use or not use interval interrupts 2 000C1H Setting of LVD operating mode Interrupt Reset mode Reset mode Break mode LVD is OFF using the external reset input of the RESETB pin Setting of ...

Page 1131: ...ption bytes 000C3H 500004H Control of flash data protection when debugging on chip Level0 Allows read write erase operations on flash data via debugger Level1 Allows chip full erase of flash data via debugger read and write operations are not allowed Level2 Operations on flash data via debugger are not allowed ...

Page 1132: ... control of the watchdog timer 0 Disables the operation of the counter stops counting after de reset 1 Allow the counter to run start counting after de reset WDCS2 WDCS1 WDCS0 Overflow time of the watchdog timer fIL 20kHz MAX 0 0 0 26 fIL 3 2ms 0 0 1 27 fIL 6 4ms 0 1 0 28 fIL 12 8ms 0 1 1 29 fIL 25 6ms 1 0 0 211 fIL 102 4ms 1 0 1 213 fIL 409 6ms 1 1 0 214 fIL 819 2ms 1 1 1 216 fIL 3276 8ms WDSTBYO...

Page 1133: ...0 Mode settings rising falling falling LVIMDS1 LVIMDS0 1 98V 1 94V 1 84V 0 0 1 1 0 1 0 2 09V 2 04V 0 1 3 13V 3 06V 0 0 2 61V 2 55V 2 45V 1 0 1 0 2 71V 2 65V 0 1 3 75V 3 67V 0 0 2 92V 2 86V 2 75V 1 1 1 0 3 02V 2 96V 0 1 4 06V 3 98V 0 0 Setting values other than those described above is prohibited Note that you must write 1 to bit4 Note 1 For details on LVD circuits refer to Chapter 32 Voltage Detec...

Page 1134: ...1 LVIMDS0 1 88V 1 84V 0 0 1 1 1 1 1 1 98V 1 94V 0 1 1 0 2 09V 2 04V 0 1 0 1 2 50V 2 45V 1 0 1 1 2 61V 2 55V 1 0 1 0 2 71V 2 65V 1 0 0 1 2 81V 2 75V 1 1 1 1 2 92V 2 86V 1 1 1 0 3 02V 2 96V 1 1 0 1 3 13V 3 06V 0 1 0 0 3 75V 3 67V 1 0 0 0 4 06V 3 98V 1 1 0 0 Setting values other than those described above is prohibited Note that you must write 1 to bit4 Note 1 For details on LVD circuits refer to Cha...

Page 1135: ...VIMDS1 LVIMDS0 1 88V 1 84V 0 0 1 1 1 0 1 1 98V 1 94V 0 1 1 0 2 09V 2 04V 0 1 0 1 2 50V 2 45V 1 0 1 1 2 61V 2 55V 1 0 1 0 2 71V 2 65V 1 0 0 1 2 81V 2 75V 1 1 1 1 2 92V 2 86V 1 1 1 0 3 02V 2 96V 1 1 0 1 3 13V 3 06V 0 1 0 0 3 75V 3 67V 1 0 0 0 4 06V 3 98V 1 1 0 0 Setting values other than those described above is prohibited Note that you must write 1 to bit4 Note 1 For details on LVD circuits refer t...

Page 1136: ...f the data sheet When the supply voltage drops it must be reset through sleep mode transfer voltage detection circuitry or external reset before the supply voltage falls below the operating voltage range The operating voltage range depends on the setting of the user option byte 000C2H 010C2H Note 1 Ignore 2 For details of LVD circuits please refer to Chapter 31 Voltage Detection Circuits 3 The det...

Page 1137: ... 0 64MHz 64MHz 1 0 0 0 0 48MHz 48MHz 0 1 0 0 0 32MHz 32MHz 0 0 0 0 0 24MHz 24MHz 0 1 0 0 1 32MHz 16MHz 0 0 0 0 1 24MHz 12MHz 0 1 0 1 0 32MHz 8MHz 0 0 0 1 0 24MHz 6MHz 0 1 0 1 1 32MHz 4MHz 0 0 0 1 1 24MHz 3MHz 0 1 1 0 0 32MHz 2MHz 0 1 1 0 1 32MHz 1MHz Other than the above Disable settings Note 1 You must write 1 to bit7 to 5 2 The operating frequency range and working voltage range vary according t...

Page 1138: ...ection Option Bytes 000C3H Address 000C3H Symbol 7 6 5 4 3 2 1 0 OCD 7 0 Address 500004H Symbol 7 6 5 4 3 2 1 0 OCDM 7 0 OCDM OCDEN Control of flash data protection 3C C3 Operations on flash data via debugger are not allowed Values other than 3C C3 C hip full erase of flash data via debugger is allowed read and write operations are not allowed Except for the above note Allows read write erase oper...

Page 1139: ...rubbing operations 35 1 FLASH control function description The BAT32G139 product contains a 256KByte capacity flash memory divided into 512 Selectors each with a capacity of 512 Bytes The BAT32G179 product contains a 512KByte capacity flash memory divided into 512 Selectors each with a capacity of 1KByte Can be used as a program memory a data memory This module supports erasure programming and rea...

Page 1140: ...pherals resource region for peripherals SRAM max 32KB data flash 2 5KB main flash region max 256KB reserved reserved reserved reserved reserved 2000_3FFFH 0050_0BFFH 0050_0200H 0003_FFFFH FFFF_FFFFH E00F_FFFFH Cortex M0 专用外设资源区 E000_0000H 4005_FFFFH 4000_0000H 2000_2FFFH 2000_0000H 0050_05FFH 0050_0000H 0001_FFFFH 0000_0000H 保留外设资源区 SRAM 最大12KB 保留保留保留数据闪存 1 5KB 保留主闪存区最大128KB Cortex M0 specif...

Page 1141: ...h mode time control register FLNVSCNT FLPRVCNT FLERVCNT Flash Wipe And Write Protection Control Register FLSECPR 35 3 1 Flash Write Protection Register FLPROT Flash protection registers are used to protect the FLASH operating control registers Address 0x40020020 After reset 00000000H R W symbol FLPROT WRP The operation register FLOPMD1 FLOPMD2 is write protected 0 Rewriting FLOPMD1 FLOPMD2 is not ...

Page 1142: ...0C reset 00H R W Symbol 7 6 5 4 3 2 1 0 FLERMD Note Chip Erase only erases the code flash area not the data flash area And chip wipe does not support hardware validation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLOPMD1 7 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLOPMD2 7 0 FLOPMD1 FLOPMD2 OPERATE 55 AA Eras...

Page 1143: ...e an error occurred in the hardware check Note EVF requires software to write 1 to clear 35 3 5 Flash full chip erase time control register FLCERCNT The FLCERCNT register allows you to set the time for flash full slice erase Address 0x40020010 After reset indefinite R W symbol FLCERCNT Load Selection of erase time settings Note 0 Use the hardware set erase time 1 Use the software set erase time F ...

Page 1144: ...tion of erase time settings Note 0 Use the hardware set erase time 1 Use the software set erase time FLSERCNT 9 0 Note When the master clock is an internal high speed OCO or when the external input clock 20M the hardware time can be set without setting FLSERCNT FLSERCNT 9 0 Software erase time setting sector erase time SERCNT 256 Tfclk which meets the hardware requirements of 4ms 31 30 29 28 27 26...

Page 1145: ...etting FLPROCNT FLPROCNT 8 0 Software erase time setting Write time PROCNT 4 Tfclk which meets the hardware requirements of 24us Load1 Write Action Setup Time Tpgs Setting Note 0 Use the hardware set write action to establish the time 1 Use the software set erase time FLPGSCNT8 0 Note When the master clock is an internal high speed OCO or when the external input clock 20M the hardware time can be ...

Page 1146: ...SECPR Register SECPR write protection 0001 00_0000H 00_0FFFH cannot be erased 0010 00_0000H 00_1FFFH cannot be erased 0011 00_0000H 00_3FFFH cannot be erased 0100 00_0000H 00_7FFFH cannot be erased 0101 00_0000H 00_FFFFH cannot be erased 0110 00_0000H 01_FFFFH cannot be erased 0111 00_0000H 03_FFFFH cannot be erased 1000 00_0000H 05_FFFFH cannot be erased 1001 00_0000H 07_FFFFH cannot be erased al...

Page 1147: ...OT to 0xF1 to de protect FLOPMD Then set FLOPMD1 to 0x55 and FLOPMD2 to 0xAA 3 Write arbitrary data to the first address of the wiped targetsector Example unsigned long 0x00000200 0xffffffff 4 Software query status register FLSTS OVF when OVF 1 indicates that the erase operation is complete 5 If hardware verification after erase ERMD1 1 is set FLSTS EV F can be determined by the software to check ...

Page 1148: ...FLSTS 35 5 Flash read The fastest finger frequency supported by flash built into this device is 32 MHz When the HCLK frequency exceeds 32MHz the hardware inserts a 1 wait period when the CPU accesses flash 35 6 Considerations for FLASH operations Flash memory has strict time requirements for the control signal of erasing and programming operation and the timing of the control signal is not qualifi...

Page 1149: ...1149 1149 Rev 1 02 Appendix Revision Record version Release date Revisions V1 00 2021 12 29 The first edition was made V1 01 2022 2 28 Added a related note for LCDB for BAT32G179 V1 02 2022 6 2 Modify the register setting instructions ...

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