Cmsemicon BAT32G1 9 Series, User Manual

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BAT32G1x9 user manual | Chapter 19 Universal serial communication unit
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19.3.9 Serial channel start register m(SSm).
The SSm register is a trigger register that sets the allowed communication/start count of each channel.
If you write "1" to each of you (SSmn), set the corresponding bit (SEmn) of the serial channel allowed
status register m(SEm) to "1" (run). Allow status). Because the SSmn bit is the trigger bit, the SSmn bit is
cleared immediately if the SEmn bit is "1".
The SSm register is set via the 16-bit memory operation instruction.
I can set the low 8 bits of the SSm register with the SSmL and through the 8-bit memory operation
instruction.
After generating the reset signal, the value of the SSm register changes to "0000H".
Figure 19-12 Format of serial channel start register m(SSm).
After reset: 0000H R/W
Symbol 15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS0
After reset: 0000H R/W
Symbol 15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS1
After reset: 0000H R/W
Symbol 15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS2
SSmn
The trigger for channel n run start
0
No triggering.
1 Place the SEmn position "1" and transfer to the Communication Standby
note
.
Note If you place the SSmn position "1"
during
communication, the communication is stopped and enters the
standby state. At this point, the values of the control registers and shift registers, the SCLKmn pin and SDOmn
pins, the FEFmn flag, the PEFmn flag, and the OVFmn flag remain in state.
Note 1 Bit15~
4 of
SS0 registers and bit15~2
of
SS1 registers
must be
set to "0" ,
the
bit15~2 of the SS 2
register
is set
to "0".
2. When receiving
UART, it must be spaced at least 4 fMCK
after the
RXEmn position
of the
SCRmn register
"1" Clock, then set SSmn to "1".
Note 1.m: Unit number (m=0~2) n: Channel number (n=0~3).
2. The read value of the SSm register is always "0000H".
0 0 0 0 0 0 0 0 0 0 0 0 SS03 SS02 SS01 SS00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS11 SS10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS21 SS20