Cmsemicon BAT32G1 9 Series, User Manual

Page: 1090 / 1149

BAT32G1x9 user manual | Chapter 30 Power-on reset circuit
www.mcu.com.cn
1090 / 1149 Rev.1.02
Figure 29-2 Timing of the generation of internal reset signals in the power-on reset circuit
and voltage detection circuit (2/3).
(2) LVD is the case of interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0 for option bytes 000C1H).
low limit of working
voltage range
V
POR
=1.51V(TYP.)
V
PDR
=1.50V(TYP.)
wait till osc precision
stablized
note1
wait till osc precision
stablized
note1
start oscillating via
software configuration
start oscillating via software
configuration
power supply
voltage(V
DD
)
0V
high speed internal
osc clock(fIH)
high speed system clock
(fMX) (Scenario of
selecting X1 oscilation)
stop
operation
CPU
reset period
(osc stop)
internal reset signal
stop
operation
V
LVDL
V
LVDH
normal operation (high speed
internal osc clock)
note2
wait time of voltage stabli POR
reset processing time
1.64ms(TYP), 3.10ms(MAX).
wait time of voltage stabli POR reset
processing time
1.64ms(TYP), 3.10ms(MAX).
LVD reset processing time
Note4 LVD reset
processing time
INTLVI
Note3
normal operation (high speed
internal osc clock)
note2
Note 1 The internal reset processing time includes the oscillation accuracy stabilization wait time for the high-speed
internal oscillator clock.
2. Can switch the CPU clock from a high-speed internal oscillator clock to a high-speed system clock or a sub-system
clock. In the
case of
an X1 clock, the oscillation settling time must be switched after the oscillation settling time is
confirmed by the state register (OSTC) of the oscillation settling time counter; In the case of using the XT1 clock, it
is necessary to switch after confirming the oscillation stabilization time using the timer function, etc.
3. After generating the interrupt request signal (INTLVI
), the
LVILV
bit of
the voltage detection level register (LVIS)
and the LVIMD position "1"
are automatically generated
. Therefore, it is important to consider the possibility that
the supply voltage
will return to a high voltage sense voltage (
V
LVDH
) or higher in a state not less than the
low voltage sense voltage (V
LVDL
), and follow it after
the inTLVI is generated "Setup steps
for confirmation
/
reset
of the operating voltage of Figure 30-7" and "Figure 30-8 interrupt." &Reset the initial setup step of the mode" to
make the settings.
4. The time until the start of normal operation except for reaching V
POR
(1.51V (TYP.)
).
In
addition to
the "Voltage
Stabilization Wait Time + POR Reset Processing Time", the
following is required after reaching the
LVD
detection level (V
LVDH
). LVD Reset Processing Time.
LVD reset processing time: 0ms~0.0701ms(MAX.
).
Note V
LVDH
, V
LVDL
: LVD sense voltage
V
POR
: The POR supply voltage rises to detect the voltage
V
PDR
: POR supply voltage drop sense voltage