Cmsemicon BAT32G1 9 Series, User Manual

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BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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FIG 20-30
example of a slave device → the master device
(Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (1/4).
(1) Start Condition ~ Address ~ Data
slave address
AD0
AD5 AD6
W
master control
IICAn
ACKDn
（
ACK
detection
）
WTIMn
(8 or 9 clock cycles
waiting)
H
ACKEn
（
ACK
control
）
MSTSn
(communicdati
on state)
STTn
(ST trigger)
H
SPTn
(ST trigger)
L
WRELn
(release from
wait)
L
INTIICAn
（
interrupt
）
TRCn
（
transmit
/reception
）
Bus
SCLAn( bus )
（
Clock line
）
SDAAn( bus )
（
data line
）
slave
IICAn
ACKDn
（
ACK detection
）
STDn
（
ST detection
）
SPDn
（
SP detection
）
WTIMn
(8 or 9 clock cycles
waiting)
ACKEn
（
ACK control
）
MSTSn
(communicdation
state)
WRELn
(release from
wait)
TRCn
（
transmit
/reception
）
H
H
L
L
注
2
start
condition
D
1
7
Note3
Note
1
：
slave device waits
：
master device and slave device wait
ACK AD4 AD3 AD2 AD1
Note: 1 To remove the wait during the master send, the IICAn
must be
written to the data instead of the WRELn position bit.
2. The time from the SDAAn pin signal drop to the SCLAn
pin signal drop is at least 4.0μs when set to standard
mode and at least
0.6μs
when set to fast mode.
3. To lift the wait during the slave receive, the IICAn
must be
placed in the "FFH" or WRELn position.