BAT32G1x9 user manual | Chapter 4 Clock generation circuit
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Rev.1.02
4.3 Control Registers of the clock generation circuit
The clock generation circuit is controlled by the following registers.
• Clock Run Mode Control Register (CMC).
• System Clock Control Register (CKC).
• Clock Operating Status Control Register (CSC).
• Oscillation settling time counter status register (OSTC).
• Oscillation Settling Time Selection Register (OSTS).
• peripheral enable register 0, 1, 2, 3(PER0, PER1, PER2, PER3)
• Subsystem Clock Mode Control Registers (OSMC).
• Frequency Selection Register (HOCODIV) for high-speed internal oscillators
• Trimming Register (HIOTRM) for high-speed internal oscillator
Note that the registers and bits assigned vary by product. You must set an initial value for the unassigned bits.
4.3.1
Clock operating mode control register (CMC).
This is the register that sets the operating mode of the X1/P121, X2/EXCLK/P122, XT1/P123,
XT2/EXCLKS/P124 pins and selects the gain of the oscillation circuit.
After the reset is released, the CMC register can only be written once via the 8-bit memory operation instruction.
This register can be read via the 8-bit memory operation instruction.
After generating a reset signal, the value of this register changes to "00H".
