Cmsemicon BAT32G1 9 Series, User Manual, Page: 811 / 1149

BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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FIG 20-31
A communication example of a slave device → a master device
(Master: Select 8 clocks to wait, Slave: Choose 9 clocks to wait) (1/3).
(1) Start Condition ~ Address ~ Data
slave address
AD0 AD1 AD2 AD3 AD4 AD5 AD6
master control
IICAn
ACKDn
（
ACKdetection
）
WTIMn
（
8 or 9 clock cycles
waiting
）
ACKEn
（
ACK control
）
MSTSn
（
communicdat
ion state
）
STTn
（
ST trigger
）
H
SPTn
（
SP trigger
）
L
WRELn
（
release from
wait
）
INTIICAn
（
interrupt
）
TRCn
（
transmit
/reception
）
bus
SCLAn(bus)
（
Clock line
）
SDAAn(bus)
（
data line
）
slave
IICAn
ACKDn
（
ACKdetection
）
STDn
（
STdetection
）
SPDn
（
SPdetection
）
WTIMn
（
8 or 9 clock cycles
waiting
）
ACKEn
（
ACK
control
）
MSTSn
（
communicdat
ion state
）
WRELn
（
release from
wait
）
INTIICAn
（
interrupt
）
TRCn
（
transmit
/reception
）
H
H
L
note2
start
condition
D
1
7
：
slave device waits
：
master device and slave device waits
ACK
note1
R
L
：
master device waits
note3
Note: 1 To remove the wait during the master's reception, the IICAn
must be
placed in the "FFH" or WRELn position.
2. The time from the SDAAn pin signal drop to the SCLAn pin signal drop is at least 4.0us
when set to standard
mode and
at least
0.6 μs
when set to fast mode.