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1313
CJ-series Instruction Execution Times and Number of Steps
Section 4-2
Execution times for most instructions differ depending on the CPU Unit used
(CJ1H-CPU6
@
H-R, CJ1H-CPU6
@
H, CJ1H-CPU4
@
H, CJ1M-CPU
@@
andCJ1G-CPU4
@
) and the conditions when the instruction is executed. The
top line for each instruction in the following table shows the minimum time
required to process the instruction and the necessary execution conditions,
and the bottom line shows the maximum time and execution conditions
required to process the instruction.
The execution time can also vary when the execution condition is OFF.
The following table also lists the length of each instruction in the
Length
(steps)
column. The number of steps required in the user program area for
each of the CJ-series instructions varies from 1 to 7 steps, depending upon
the instruction and the operands used with it. The number of steps in a pro-
gram is not the same as the number of instructions.
Note
1.
Program capacity for CJ-series PLCs is measured in steps, whereas pro-
gram capacity for previous OMRON PLCs, such as the C-series and CV-
series PLCs, was measured in words. Basically speaking, 1 step is equiv-
alent to 1 word. The amount of memory required for each instruction, how-
ever, is different for some of the CJ-series instructions, and inaccuracies
will occur if the capacity of a user program for another PLC is converted for
a CJ-series PLC based on the assumption that 1 word is 1 step. Refer to
the information at the end of
4-1 CS-series Instruction Execution Times
and Number of Steps
for guidelines on converting program capacities from
previous OMRON PLCs.
2.
Most instructions are supported in differentiated form (indicated with
↑
,
↓
,
@, and %). Specifying differentiation will increase the execution times by
the following amounts.
3.
Use the following times as guidelines when instructions are not executed.
4-2-1
Sequence Input Instructions
Symbol
CJ1-H
CJ1M
CJ1
CPU6
@
H-R
CPU6
@
H
CPU4
@
H
CPU
@@
CPU4
@
↑
or
↓
+0.24
µ
s
+0.24
µ
s
+0.32
µ
s
+0.5
µ
s
+0.45
µ
s
@ or %
+0.24
µ
s
+0.24
µ
s
+0.32
µ
s
+0.5
µ
s
+0.33
µ
s
CJ1-H
CJ1M
CJ1
CPU6
@
H-R
CPU6
@
H
CPU4
@
H
CPU
@@
CPU4
@
Approx.
0.1
µ
s
Approx.
0.1
µ
s
Approx.
0.2
µ
s
Approx. 0.2
to 0.5
µ
s
Approx. 0.2
to 0.4
µ
s
Instruction
Mne-
monic
Code Length
(steps)
ON execution time (
µ
s)
Conditions
CPU6
@
H-R
CPU6
@
H
CPU4
@
H
CPU4
@
CJ1M
exclud-
ing
CPU11/
21
CJ1M
CPU11/
21
LOAD
LD
---
1
0.016
0.02
0.04
0.08
0.10
0.10
---
!LD
---
2
+21.14
+21.14
+21.16
+21.16
+24.10
+28.07
Increase for immedi-
ate refresh
LOAD NOT
LD NOT
---
1
0.016
0.02
0.04
008
0.10
0.10
---
!LD NOT ---
2
+21.14
+21.14
+21.16
+21.16
+24.10
+28.07
Increase for immedi-
ate refresh
AND
AND
---
1
0.016
0.02
0.04
0.08
0.10
0.10
---
!AND
---
2
+21.14
+21.14
+21.16
+21.16
+24.10
+28.07
Increase for immedi-
ate refresh
Содержание SYSMAC CS1D-CPU**
Страница 3: ...iv...
Страница 29: ...xxx...
Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
Страница 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Страница 1391: ...1352 ASCII Code Table Appendix A...