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220
Sequence Control Instructions
Section 3-5
Timing Chart
• Operation of Differentiated Instructions in an MILR(518) Interlock
If there is a differentiated instruction (DIFU, DIFD, or instruction with a @
or % prefix) between MILR(518) and the corresponding MILC(519), that in-
struction
will not
be executed after the interlock is cleared even if the dif-
ferentiation condition of the instruction was established. (The system
compares the execution condition’s status in the cycle when the interlock
started to its status in the cycle when the interlock was cleared.)
In the same way, a differentiated instruction will not be executed if its exe-
cution condition is established at the same time that the interlock is started
or cleared.
• Example
When a DIFFERENTIATE UP (DIFU(013)) instruction is being used
and the input condition is OFF when the interlock starts and ON when
the interlock is cleared, DIFU(013)
will not
be executed when the in-
terlock is cleared.
ON
000000
000001
001000
OFF
OFF
ON
ON
OFF
ON
OFF
1 cycle
DIFU(013) is executed.
MILH(517) interlock
Not interlocked
Interlocked
Not interlocked
Status (OFF) at
start of interlock
Differentiation condition established
Status (ON) when
interlock is cleared
MILR
0
MILC
0
DIFU
001000
000000
000001
1. When CIO 000000 is OFF (interlock starts), the DIFU's CIO 000001 input condition is OFF.
2. The DIFU's CIO 000001 input condition goes from OFF to ON while CIO 000000 is OFF (DIFU interlocked),
3. When CIO 000000 goes from OFF to ON (interlock cleared), DIFU is not executed even though CIO 000001 is still ON.
Содержание SYSMAC CS1D-CPU**
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Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
Страница 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
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