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High-speed Counter/Pulse Output Instructions
Section 3-21
Flags
Examples
■
Example 1
When CIO 000000 turns ON in the following programming example,
CTBL(882) registers a range comparison table for high-speed counter 0 and
starts comparison. When CIO 000001 turns ON, PRV(881) reads the range
comparison results at that time and stores them in CIO 0100.
■
Example 2
When CIO 000100 turns ON in the following programming example, PRV(881)
reads the frequency of the pulse being input to high-speed counter 0 at that
time and stores it as a hexadecimal value in D00200 and D00201.
3-21-3 COUNTER FREQUENCY CONVERT: PRV2(883)
Purpose
PRV2(883) reads the pulse frequency input from a high-speed counter and
either converts the frequency to a rotational speed or converts the counter PV
to the total number of revolutions. The result is output to the destination words
as 8-digit hexadecimal. Pulses can be input from high-speed counter 0 only.
This instruction is supported only by the CJ1M-CPU21/22/23 CPU Unit Ver.
2.0 or later.
Name
Label
Operation
Error Flag
ER
ON if the specified range for P or C is exceeded.
ON if the combination of P and C is not allowed.
ON if reading range comparison results is specified even
though range comparison is not being executed.
ON if reading the output frequency is specified for any-
thing except for high-speed counter 0.
ON if specified for a port not set for a high-speed counter.
ON if executed for a port not set for an interrupt input in
counter mode.
@CTBL
#0000
#0001
D00100
000000
@PRV
#0010
#0002
0100
000001
Range comparison table
registration and comparison start
High-speed counter input 0
Read range comparison results
High-speed counter input 0
PRV
#0010
#0003
D00200
000100
High-speed counter input 0
Read input frequency
Содержание SYSMAC CS1D-CPU**
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Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
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Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
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