![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268202.webp)
163
Sequence Input Instructions
Section 3-3
Example
3-3-2
LOAD NOT: LD NOT
Purpose
Indicates a logical start and creates an ON/OFF execution condition based on
the reverse of the ON/OFF status of the specified operand bit.
Ladder Symbol
Variations
Note
1.
The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @LD NOT, %LD NOT, !@LD NOT, and !%LD NOT.
2.
Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3.
Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.
Instruction
Operand
LD
000000
LD
000001
LD
000002
AND
000003
OR LD
---
AND LD
---
LD NOT
000004
AND
000005
OR LD
---
OUT
000100
OR LD
AND LD
OR LD
Bus bar
Starting point of block
Variations
Restarts Logic and Creates ON Each Cycle Operand
Bit is OFF
LD NOT
Restarts Logic and Creates ON Once for Upward
Differentiation (See note 1.)
@LD NOT
Restarts Logic and Creates ON Once for Downward
Differentiation (See note 1.)
%LD NOT
Immediate Refreshing Specification (See note 2.)
!LD NOT
Combined
Variations
Refreshes Input Bit, Restarts Logic, and Creates ON
Once for Upward Differentiation (See note 3.)
!@LD NOT
Refreshes Input Bit, Restarts Logic, and Creates ON
Once for Downward Differentiation (See note 3.)
!%LD NOT
Содержание SYSMAC CS1D-CPU**
Страница 3: ...iv...
Страница 29: ...xxx...
Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
Страница 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Страница 1391: ...1352 ASCII Code Table Appendix A...