![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268070.webp)
31
Instruction Functions
Section 2-2
INTERLOCK
CLEAR
ILC
003
All outputs between IL(002) and ILC(003) are interlocked when the
execution condition for IL(002) is OFF. IL(002) and ILC(003) are nor-
mally used in pairs.
Output
Not required
210
MULTI-INTER-
LOCK DIFFER-
ENTIATION
HOLD
MILH
517
CS/CJ
-series CPU
Unit Ver. 2.0 or later
only
When the execution condition for MILH(517) is OFF, the outputs for all
instructions between that MILH(517) instruction and the next
MILC(519) instruction are interlocked. MILH(517) and MILC(519) are
used as a pair.
MILH(517)/MILC(519) interlocks can be nested (e.g., MILH(517)—
MILH(517)—MILC(519)—MILC(519)).
If there is a differentiated instruction (DIFU, DIFD, or instruction with a
@ or% prefix) between MILH(517) and the corresponding MILC(519),
that instruction will be executed after the interlock is cleared if the dif-
ferentiation condition of the instruction was established while it was
interlocked.
Output
Required
214
MULTI-INTER-
LOCK DIFFER-
ENTIATION
RELEASE
MILR
518
CS/CJ
-series CPU
Unit Ver. 2.0 or later
only
When the execution condition for MILR(518) is OFF, the outputs for all
instructions between that MILR(518) instruction and the next
MILC(519) instruction are interlocked.MILR(518) and MILC(519) are
used as a pair.
MILR(518)/MILC(519) interlocks can be nested (e.g., MILR(518)—
MILR(518)—MILC(519)—MILC(519)).
If there is a differentiated instruction (DIFU, DIFD, or instruction with a
@ or % prefix) between MILR(518) and the corresponding MILC(519),
that instruction will not be executed after the interlock is cleared even if
the differentiation condition of the instruction was established.
Output
Required
214
MULTI-INTER-
LOCK CLEAR
MILC
519
CS/CJ
-series CPU
Unit Ver. 2.0 or later
only
Clears an interlock started by an MILH(517) or MILR(518) with the
same interlock number.
All outputs between MILH(517)/MILR(518) and the corresponding
MILC(519) with the same interlock number are interlocked when the
execution condition for MILH(517)/MILR(518) is OFF.
Output
Not required
214
JUMP
JMP
004
Output
Required
228
CONDITIONAL
JUMP
CJP
510
Output
Required
232
Instruction
Mnemonic
Code
Symbol/Operand
Function
Location
Execution
condition
Page
ILC(003)
MILH (517)
N
D
N
: Interlock number
D
: Interlock Status Bit
MILR (518)
N
D
N
: Interlock number
D
: Interlock Status Bit
MILC (519)
N
N
: Interlock number
JMP(004)
N
N
:
Jump number
When the execution condition for JMP(004) is OFF, program
execution jumps directly to the first JME(005) in the program with
the same jump number. JMP(004) and JME(005) are used in pairs.
Execution condition
Instructions
jumped
Instructions in this section
are not executed and out-
put status is maintained.
The instruction execution
time for these instructions
is eliminated.
Instructions
executed
CJP(510)
N
N
:
Jump number
The operation of CJP(510) is the basically the opposite of JMP(004).
When the execution condition for CJP(510) is ON, program execution
jumps directly to the first JME(005) in the program with the same jump
number. CJP(510) and JME(005) are used in pairs.
Execution
condition OFF
Execution
condition ON
Instructions
jumped
Instructions in this section
are not executed and out-
put status is maintained.
The instruction execution
time for these instructions
is eliminated.
Instructions
executed
Содержание SYSMAC CS1D-CPU**
Страница 3: ...iv...
Страница 29: ...xxx...
Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
Страница 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Страница 1391: ...1352 ASCII Code Table Appendix A...