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Interrupt Control Instructions
Section 3-20
Operation of CLI(691)
If an interrupt input is received while a different I/O interrupt task is being exe-
cuted, the input’s interrupt number is recorded internally until the current task
and any higher priority tasks have been completed. CLI(691) can be used to
clear recorded interrupts before they are executed, but cannot clear interrupt
tasks that are being executed.
In this example, CLI(691) uses the contents of D00101 to clear all of the
recorded interrupt inputs from Interrupt Input Unit 0 except inputs 0, 2, and 3.
After completion of interrupt task 3, recorded interrupts are executed in order
of their priority. Since an input from interrupt input 0 was recorded, I/O inter-
rupt task 0 (interrupt task 100) will be executed when task 3 is completed.
Interrupt input 1 is not retained by CLI(691), so that input is cleared.
If interrupt inputs 0 through 3 all go ON and CLI(691) is not executed, all of the
inputs will be recorded and the interrupt tasks will be executed in order after
interrupt task 3 is completed. (The interrupt tasks are executed in order of
their priority, from the lowest interrupt number to the highest.)
Note
1.
It is not always necessary to use CLI(691).
2.
When CLI(691) is not executed, all of the I/O interrupt inputs received dur-
ing the execution of an interrupt task will be recorded. If a recorded input
is received again, the later input will be ignored.
3.
When two or more I/O interrupt inputs are recorded, they are executed in
order of their priority. The order in which the recorded inputs were received
is irrelevant.
F
2
Interrupt inputs from Unit 0
Interrupt clear/retain settings
1=Clear recorded input 0=Retain recorded input
Interrupt input 0
Interrupt input 1
Interrupt input 2
Recorded interrupts
I/O Interrupt task
Task 3
Task 0
Task 3
CLI(691) is executed. Interrupt inputs 0 and 3
are retained and input 1 is cleared.
Already recorded, so
later input is ignored.
Interrupt input 1 is cleared by CLI(691).
Interrupt task 3
Interrupt task 0
Interrupt task 1
Interrupt task 2
Interrupt task 3
Содержание SYSMAC CS1D-CPU**
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