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165
Sequence Input Instructions
Section 3-3
Flags
There are no flags affected by this instruction.
Precautions
Immediate refreshing (!) can be specified for LD NOT. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted for Basic Input Units (but not Basic Input Units on Slave Racks or for
C200H Group 2 Multi-point Input Units).
Example
3-3-3
AND: AND
Purpose
Takes a logical AND of the status of the specified operand bit and the current
execution condition.
Ladder Symbol
Variations
Note
Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.
Applicable Program Areas
Instruction
Operand
LD
000000
LD
000001
LD
000002
AND
000003
OR LD
---
AND LD
---
LD NOT
000004
AND
000005
OR LD
---
OUT
000100
OR LD
AND LD
OR LD
Variations
Creates ON Each Cycle AND Result is ON
AND
Creates ON Once for Upward Differentiation
@AND
Creates ON Once for Downward Differentiation
%AND
Immediate Refreshing Specification (See note.)
!AND
Combined
Variations
Refreshes Input Bit and Creates ON Once for
Upward Differentiation (See note.)
!@AND
Refreshes Input Bit and Creates ON Once for
Downward Differentiation (See note.)
!%AND
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Содержание SYSMAC CS1D-CPU**
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Страница 185: ...146 List of Instructions by Function Code Section 2 4...
Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
Страница 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Страница 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Страница 1391: ...1352 ASCII Code Table Appendix A...