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416
Increment/Decrement Instructions
Section 3-10
3-10-4 DOUBLE DECREMENT BINARY: – –L(593)
Purpose
Decrements the 8-digit hexadecimal content of the specified words by 1.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Description
The – –L(593) instruction subtracts 1 from the 8-digit hexadecimal content of
Wd+1 and Wd. The content of the specified words will be decremented by 1
every cycle as long as the execution condition of – –L(593) is ON. When the
up-differentiated variation of this instruction (@– –L(593)) is used, the content
− −
L(593)
Wd
Wd
:
First word
Variations
Executed Each Cycle for ON Condition
– –L(593)
Executed Once for Upward Differentiation
@– –L(593)
Executed Once for Downward
Differentiation
Not supported
Immediate Refreshing Specification
Not supported
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
Wd
CIO Area
CIO 0000 to CIO 6142
Work Area
W000 to W510
Holding Bit Area
H000 to H510
Auxiliary Bit Area
A448 to A958
Timer Area
T0000 to T4094
Counter Area
C0000 to C4094
DM Area
D00000 to D32766
EM Area without bank
E00000 to E32766
EM Area with bank
En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM
addresses in binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
Data Registers
---
Index Registers
IR0 to IR15
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Содержание SYSMAC CS1D-CPU**
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Страница 193: ...154 3 35 4 MOVE BIT MOVBC 568 1274 3 35 5 BIT COUNTER BCNTC 621 1276 3 35 6 GET VARIABLE ID GETID 286 1278...
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