ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
705
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK)
SPIx_CLK pin
SPIx_MOSIz pin
SPIx_MISOz pin
TX[6]
TX[0]
TX[7]
TX[6]
LSB
TX[0]
RX[6]
RX[0]
RX[6]
LSB
RX[0]
MSB
RX[7]
RX[7]
MSB
TX[7]
SPIx_SSy pin
CLKPOL=0
CLKPOL=1
SSACTPOL=0
SSACTPOL=1
Note:
Slave Mode
Registers Setting: SLAVE=1, LSB=0, DWIDTH=0x08
CLKPOL=0, TXNEG=1, RXNEG=0 or CLKPOL=1, TXNEG=0, RXNEG=1
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)
Figure 6.14-37 SPI Timing in Slave Mode
SPIx_CLK pin
SPIx_MOSIz pin
SPIx_MISOz pin
TX[1]
TX[7]
TX[0]
TX[1]
MSB
TX[7]
RX[1]
RX[7]
RX[1]
MSB
RX[7]
LSB
RX[0]
RX[0]
LSB
TX[0]
SPIx_SSy pin
CLKPOL=0
CLKPOL=1
SSACTPOL=0
SSACTPOL=1
Note:
Slave Mode
Registers Setting: SLAVE=1, LSB=1, DWIDTH=0x08
CLKPOL=0, TXNEG=0, RXNEG=1 or CLKPOL=1, TXNEG=1, RXNEG=0
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)
Figure 6.14-38 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK)
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