ISD94100 Series Technical Reference Manual
Sep 9, 2019
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6.20.6 Register Map
R
: read only,
W
: write only,
R/W
: both read and write.
Register
Offset
R/W Description
Reset Value
VAD Base Address:
VAD_BA = 0x4006_3100
VAD_SINCCTL
0x00
R/W VAD SINC Filter Control Register
0x0000_0008
VAD_BIQCTL0
0x04
R/W VAD Biquad Filter Control Register 0
0x0000_0000
VAD_BIQCTL1
0x08
R/W VAD Biquad Filter Control Register 1
0x0000_0000
VAD_BIQCTL2
0x0C
R/W VAD Biquad Filter Control Register 2
0x0000_0000
VAD_CTL0
0x10
R/W VAD Control Register 0
0x0007_00CC
VAD_CTL1
0x14
R/W VAD Control Register 1
0x0000_7FFF
VAD_CTL2
0x18
R/W VAD Control Register 2
0x0000_0000
VAD_CTL3
0x1C
R/W VAD Control Register 3
0x0000_7FFF
VAD_STATUS0
0x20
R
VAD Status Read-Back Register 0
0x0000_0000
VAD_STATUS1
0x24
R
VAD Status Read-Back Register 1
0x0000_0000
Note:
1.
Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2.
The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with
other than reset values may produce undefined results.
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