ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
281
of 928
Rev1.09
IS
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0
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ICA
L
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NCE
M
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U
AL
Start Source Address Register (PDMA_DSCTn_SA)
Register
Offset
R/W Description
Reset Value
PDMA_DSCT0_SA
P 0x04
R/W Source Address Register of PDMA Channel 0
0xXXXX_XXXX
PDMA_DSCT1_SA
P 0x14
R/W Source Address Register of PDMA Channel 1
0xXXXX_XXXX
PDMA_DSCT2_SA
P 0x24
R/W Source Address Register of PDMA Channel 2
0xXXXX_XXXX
PDMA_DSCT3_SA
P 0x34
R/W Source Address Register of PDMA Channel 3
0xXXXX_XXXX
PDMA_DSCT4_SA
P 0x44
R/W Source Address Register of PDMA Channel 4
0xXXXX_XXXX
PDMA_DSCT5_SA
P 0x54
R/W Source Address Register of PDMA Channel 5
0xXXXX_XXXX
PDMA_DSCT6_SA
P 0x64
R/W Source Address Register of PDMA Channel 6
0xXXXX_XXXX
PDMA_DSCT7_SA
P 0x74
R/W Source Address Register of PDMA Channel 7
0xXXXX_XXXX
PDMA_DSCT8_SA
P 0x84
R/W Source Address Register of PDMA Channel 8
0xXXXX_XXXX
PDMA_DSCT9_SA
P 0x94
R/W Source Address Register of PDMA Channel 9
0xXXXX_XXXX
PDMA_DSCT10_SA
P 0xA4
R/W Source Address Register of PDMA Channel 10
0xXXXX_XXXX
PDMA_DSCT11_SA
P 0xB4
R/W Source Address Register of PDMA Channel 11
0xXXXX_XXXX
PDMA_DSCT12_SA
P 0xC4
R/W Source Address Register of PDMA Channel 12
0xXXXX_XXXX
PDMA_DSCT13_SA
P 0xD4
R/W Source Address Register of PDMA Channel 13
0xXXXX_XXXX
PDMA_DSCT14_SA
P 0xE4
R/W Source Address Register of PDMA Channel 14
0xXXXX_XXXX
PDMA_DSCT15_SA
P 0xF4
R/W Source Address Register of PDMA Channel 15
0xXXXX_XXXX
31
30
29
28
27
26
25
24
SA
23
22
21
20
19
18
17
16
SA
15
14
13
12
11
10
9
8
SA
7
6
5
4
3
2
1
0
SA
Bits
Description
[31:0]
SA
PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.
Note:
The reset value of this field will be different every time powered chip.
Содержание ISD94100 Series
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