ISD94100 Series Technical Reference Manual
Sep 9, 2019
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[8]
EINT0
External Interrupt 0 NMI Source Enable (Write Protected)
0 = External interrupt 0 NMI source Disabled.
1 = External interrupt 0 NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[7]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[6]
RTC_INT
RTC NMI Source Enable (Write Protected)
0 = RTC NMI source Disabled.
1 = RTC NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[5]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[4]
CLKFAIL
Clock Fail Detected NMI Source Enable (Write Protected)
0 = Clock fail detected interrupt NMI source Disabled.
1 = Clock fail detected interrupt NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[3]
SRAM_PERR
SRAM Parity Check Error NMI Source Enable (Write Protected)
0 = SRAM parity check error NMI source Disabled.
1 = SRAM parity check error NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[2]
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable (Write Protected)
0 = Power-down mode wake-up NMI source Disabled.
1 = Power-down mode wake-up NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[1]
IRC_INT
IRC TRIM NMI Source Enable (Write Protected)
0 = IRC TRIM NMI source Disabled.
1 = IRC TRIM NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[0]
BODOUT
BOD NMI Source Enable (Write Protected)
0 = BOD NMI source Disabled.
1 = BOD NMI source Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
Содержание ISD94100 Series
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