ISD94100 Series Technical Reference Manual
Sep 9, 2019
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IRQ64 ~ IRQ95 Set-Pending Control Register (NVIC_ISPR2)
Register
Offset
R/W Description
Reset Value
NVIC_ISPR2
0xE000E208
R/W IRQ64 ~ IRQ95 Set-Pending Control Register
0x0000_0000
31
30
29
28
27
26
25
24
SETPEND
23
22
21
20
19
18
17
16
SETPEND
15
14
13
12
11
10
9
8
SETPEND
7
6
5
4
3
2
1
0
SETPEND
Bits
Description
[31:0]
SETPEND
Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state, and show
which interrupts are pending
Write Operation:
0 = No effect.
1 = Changes interrupt state to pending.
Read Operation:
0 = Interrupt is not pending.
1 = Interrupt is pending.
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