ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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Register
Offset
R/W Description
Reset Value
PDMA Base Address:
PDMA_BA = 0x4000_8000
PDMA_REQSEL0_3
P 0x480 R/W PDMA Request Source Select Register 0
0x0000_0000
PDMA_REQSEL4_7
P 0x484 R/W PDMA Request Source Select Register 1
0x0000_0000
PDMA_REQSEL8_11
P 0x488 R/W PDMA Request Source Select Register 2
0x0000_0000
PDMA_REQSEL12_15
P 0x48C R/W PDMA Request Source Select Register 3
0x0000_0000
PDMA_STCR0
P 0x500 R/W Stride Transfer Count Register of PDMA Channel 0
0x0000_0000
PDMA_ASOCR0
P 0x504 R/W Address Stride Offset Register of PDMA Channel 0
0x0000_0000
PDMA_STCR1
P 0x508 R/W Stride Transfer Count Register of PDMA Channel 1
0x0000_0000
PDMA_ASOCR1
P 0x50C R/W Address Stride Offset Register of PDMA Channel 1
0x0000_0000
PDMA_STCR2
P 0x510 R/W Stride Transfer Count Register of PDMA Channel 2
0x0000_0000
PDMA_ASOCR2
P 0x514 R/W Address Stride Offset Register of PDMA Channel 2
0x0000_0000
PDMA_STCR3
P 0x518 R/W Stride Transfer Count Register of PDMA Channel 3
0x0000_0000
PDMA_ASOCR3
P 0x51C R/W Address Stride Offset Register of PDMA Channel 3
0x0000_0000
PDMA_STCR4
P 0x520 R/W Stride Transfer Count Register of PDMA Channel 4
0x0000_0000
PDMA_ASOCR4
P 0x524 R/W Address Stride Offset Register of PDMA Channel 4
0x0000_0000
PDMA_STCR5
P 0x528 R/W Stride Transfer Count Register of PDMA Channel 5
0x0000_0000
PDMA_ASOCR5
P 0x52C R/W Address Stride Offset Register of PDMA Channel 5
0x0000_0000
Note:
1.
Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2.
The reserved register fields that listed in register addresses 0x0 to 0x140 must be written as 0.
Writing reserved fields with other than 0 may produce undefined results.
3.
The reserved register fields that listed in register addresses greater than 0x400 must be written with reset value.
Writing reserved fields with other than reset value may produce undefined results.
Содержание ISD94100 Series
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