ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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ICA
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NCE
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IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER0)
Register
Offset
R/W Description
Reset Value
NVIC_ICER0
0xE000E180
R/W IRQ0 ~ IRQ31 Clear-Enable Control Register
0x0000_0000
31
30
29
28
27
26
25
24
CALENA
23
22
21
20
19
18
17
16
CALENA
15
14
13
12
11
10
9
8
CALENA
7
6
5
4
3
2
1
0
CALENA
Bits
Description
[31:0]
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are
enabled.
Write Operation:
0 = No effect.
1 = Interrupt Disabled.
Read Operation:
0 = Interrupt Disabled.
1 = Interrupt Enabled.
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