ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
290
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
PDMA Transfer Stop Control Register (PDMA_STOP)
Register
Offset
R/W Description
Reset Value
PDMA_STOP
P 0x404 W
PDMA Transfer Stop Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
STOP15
STOP14
STOP13
STOP12
STOP11
STOP10
STOP9
STOP8
7
6
5
4
3
2
1
0
STOP7
STOP6
STOP5
STOP4
STOP3
STOP2
STOP1
STOP0
Bits
Description
[31:16]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[15]
STOP15
PDMA Channel 15 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 15 transfer. When user sets STOP15 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN15 (PDMA_CHCTL [15]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 15 transfer.
[14]
STOP14
PDMA Channel 14 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 14 transfer. When user sets STOP14 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN14 (PDMA_CHCTL [14]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 14 transfer.
[13]
STOP13
PDMA Channel 13 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 13 transfer. When user sets STOP13 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN13 (PDMA_CHCTL [13]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 13 transfer.
[12]
STOP12
PDMA Channel 12 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 12 transfer. When user sets STOP12 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN12 (PDMA_CHCTL [12]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 12 transfer.
Содержание ISD94100 Series
Страница 528: ...ISD94100 Series Technical Reference Manual Sep 9 2019 Page 528 of 928 Rev1 09 ISD94100 SERIES TECHNICAL REFERENCE MANUAL...
Страница 626: ...ISD94100 Series Technical Reference Manual Sep 9 2019 Page 626 of 928 Rev1 09 ISD94100 SERIES TECHNICAL REFERENCE MANUAL...
Страница 702: ...ISD94100 Series Technical Reference Manual Sep 9 2019 Page 702 of 928 Rev1 09 ISD94100 SERIES TECHNICAL REFERENCE MANUAL...
Страница 875: ...ISD94100 Series Technical Reference Manual Sep 9 2019 Page 875 of 928 Rev1 09 ISD94100 SERIES TECHNICAL REFERENCE MANUAL...