ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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USB Buffer Segmentation Register (USBD_BUFSEGx)
Register
Offset
R/W Description
Reset Value
USBD_BUFSEG0
0x500
R/W Endpoint 0 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG1
0x510
R/W Endpoint 1 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG2
0x520
R/W Endpoint 2 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG3
0x530
R/W Endpoint 3 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG4
0x540
R/W Endpoint 4 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG5
0x550
R/W Endpoint 5 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG6
0x560
R/W Endpoint 6 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG7
0x570
R/W Endpoint 7 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG8
0x580
R/W Endpoint 8 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG9
0x590
R/W Endpoint 9 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG10
0x5A0
R/W Endpoint 10 Buffer Segmentation Register
0x0000_0000
USBD_BUFSEG11
0x5B0
R/W Endpoint 11 Buffer Segmentation Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
BUFSEG
7
6
5
4
3
2
1
0
BUFSEG
Reserved
Bits
Description
[31:9]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[8:3]
BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting
address The effective starting address of the endpoint is
USBD_SRAM a { BUFSEG, 3’b000}
Where the USBD_SRAM address = 0x100h.
Refer to the section 6.18.5.7 for the endpoint SRAM structure and its description.
[2:0]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
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