ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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6.2.10 Register Map
R:
read only,
W:
write only,
R/W:
both read and write
Register
Offset
R/W Description
Reset Value
SYS Base Address:
SYS_BA = 0x4000_0000
SYS_PDID
0x00
R
Part Device Identification Number Register
0x1DXX_05XX
[1]
SYS_RSTSTS
0x04
R/W System Reset Status Register
0x0000_0043
SYS_IPRST0
0x08
R/W Peripheral Reset Control Register 0
0x0000_0000
SYS_IPRST1
0x0C
R/W Peripheral Reset Control Register 1
0x0000_0000
SYS_IPRST2
0x10
R/W Peripheral Reset Control Register 2
0x0000_0000
SYS_BODCTL
0x18
R/W Brown-Out Detector Control Register
0x000X_038X
SYS_PORCTL
0x24
R/W Power-On-Reset Controller Register
0x0000_0000
SYS_USBPHY
0x2C
R/W USB PHY Control Register
0x0000_0000
SYS_GPA_MFPL
0x30
R/W GPIOA Low Byte Multiple Function Control Register 0x0000_0000
SYS_GPA_MFPH
0x34
R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000
SYS_GPB_MFPL
0x38
R/W GPIOB Low Byte Multiple Function Control Register 0x0110_0000
SYS_GPB_MFPH
0x3C
R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000
SYS_GPC_MFPL
0x40
R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000
SYS_GPC_MFPH
0x44
R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000
SYS_GPD_MFPL
0x48
R/W GPIOD Low Byte Multiple Function Control Register 0x0000_0000
SYS_GPD_MFPH
0x4C
R/W GPIOD High Byte Multiple Function Control Register 0x0000_0011
SYS_SRAM_INTCTL
0xC0
R/W System SRAM Interrupt Enable Control Register
0x0000_0000
SYS_SRAM_STATUS
0xC4
R/W System SRAM Parity Error Status Register
0x0000_0000
SYS_SRAM_ERRADDR
0xC8
R
System SRAM Parity Check Error Address Register 0x0000_0000
SYS_IRCTCTL
0xF0
R/W HIRC Trim Control Register
0x0000_0000
SYS_IRCTIEN
0xF4
R/W HIRC Trim Interrupt Enable Register
0x0000_0000
SYS_IRCTISTS
0xF8
R/W HIRC Trim Interrupt Status Register
0x0000_0000
SYS_REGLCTL
0x100
R/W Register Lock Control Register
0x0000_0000
SYS_RCADJ
0x110
R/W HIRC Trim Value Register
0x0000_0XXX
Note:
1.
Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2.
The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with
other than reset values may produce undefined results.
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