ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
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Rev1.09
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6.14.8 Register Map
R
: read only,
W
: write only,
R/W
: both read and write
Register
Offset
R/W
Description
Reset Value
SPI Base Address:
SPI0_BA = 0x4006_0000
SPI1_BA = 0x4006_1000
SPI2_BA = 0x4006_2000
SPI0_CTL
0x00
R/W SPI0 Control Register
0x0000_0034
SPI0_CLKDIV
0x04
R/W SPI0 Clock Divider Register
0x0000_0000
SPI0_SSCTL
0x08
R/W SPI0 Slave Select Control Register
0x0000_0000
SPI0_PDMACTL
0x0C
R/W SPI0 PDMA Control Register
0x0000_0000
SPI0_FIFOCTL
0x10
R/W SPI0 FIFO Control Register
0x4400_0000
SPI0_STATUS
0x14
R/W SPI0 Status Register
0x0005_0110
SPI0_TX
0x20
W
SPI0 Data Transmit Register
0x0000_0000
SPI0_RX
0x30
R
SPI0 Data Receive Register
0x0000_0000
SPI1_CTL
0x00
R/W SPI1 Control Register
0x0000_0034
SPI1_CLKDIV
0x04
R/W SPI1 Clock Divider Register
0x0000_0000
SPI1_SSCTL
0x08
R/W SPI1 Slave Select Control Register
0x0000_0000
SPI1_PDMACTL
0x0C
R/W SPI1 PDMA Control Register
0x0000_0000
SPI1_FIFOCTL
0x10
R/W SPI1 FIFO Control Register
0x2200_0000
SPI1_STATUS
0x14
R/W SPI1 Status Register
0x0005_0110
SPI1_TX
0x20
W
SPI1 Data Transmit Register
0x0000_0000
SPI1_RX
0x30
R
SPI1 Data Receive Register
0x0000_0000
SPI1_I2SCTL
0x60
R/W SP1 I2S Control Register
0x0000_0000
SPI1_I2SCLK
0x64
R/W SPI1 I2S Clock Divider Control Register
0x0000_0000
SPI1_I2SSTS
0x68
R/W SPI1 I2S Status Register
0x0005_0100
SPI2_CTL
0x00
R/W SPI2 Control Register
0x0000_0034
SPI2_CLKDIV
0x04
R/W SPI2 Clock Divider Register
0x0000_0000
SPI2_SSCTL
0x08
R/W SPI2 Slave Select Control Register
0x0000_0000
SPI2_PDMACTL
0x0C
R/W SPI2 PDMA Control Register
0x0000_0000
SPI2_FIFOCTL
0x10
R/W SPI2 FIFO Control Register
0x2200_0000
SPI2_STATUS
0x14
R/W SPI2 Status Register
0x0005_0110
SPI2_TX
0x20
W
SPI2 Data Transmit Register
0x0000_0000
SPI2_RX
0x30
R
SPI2 Data Receive Register
0x0000_0000
SPI2_I2SCTL
0x60
R/W SPI2 I2S Control Register
0x0000_0000
SPI2_I2SCLK
0x64
R/W SPI2 I2S Clock Divider Control Register
0x0000_0000
Содержание ISD94100 Series
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