ISD94100 Series Technical Reference Manual
Sep 9, 2019
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shown in Figure 6.8-34.
Among the above described brake sources, the brake source coming from system fail can still be
specified to several different system fail conditions. These conditions include clock fail, Brown-out
detect, SRAM parity check error and Core lockup. Figure 6.8-35 shows that by setting
corresponding enable bits, the enabled system fail condition can be one of the sources to issue the
Brake system fail to the PWM brake.
BRKLTRG0 (PWM_SWBRK[8])
BRKP0EEN (PWM_BRKCTL0[4])
Brake Noise Filter
BRKP1EEN (PWM_BRKCTL0[5])
PWM0_BRAKE0
Brake Noise Filter
PWM0_BRAKE1
Brake
Function
Brake
Function
Edge Detect
Brake Source
Level Detect
Brake Source
Brake System Fail
SYSEBEN (PWM_BRKCTL0[7])
EADCRM
EADCEBEN (PWM_BRKCTL0[20])
BRKP0LEN (PWM_BRKCTL0[12])
Brake Noise Filter
BRKP1LEN (PWM_BRKCTL0[13])
Brake Noise Filter
Brake System Fail
SYSLBEN (PWM_BRKCTL0[15])
EADCRM
EADCLBEN (PWM_BRKCTL0[28])
BRKETRG0 (PWM_SWBRK[0])
Figure 6.8-34 Brake Source Block Diagram
CSSBRKEN (PWM_FAILBRK[0])
Clock Fail
BODBRKEN (PWM_FAILBRK[1])
Brown-Out Detect
RAMBRKEN (PWM_FAILBRK[2])
SRAM Parity Error
CORBRKEN (PWM_FAILBRK[3])
Core Lockup
Brake Source
Brake System
Fail
Figure 6.8-35 Brake System Fail Block Diagram
6.8.5.24 Polarity Control
Each PWM port, from PWM_CH0 to PWM_CH5, has an independent polarity control module to
configure the polarity of the active state of the PWM output. By default, the PWM output is active
high. This implies the PWM OFF state is low and ON state is high. This definition is variable through
setting the PWM Negative Polarity Control Register (PWM_POLCTL), for each individual PWM
channel. Figure 6.8-36 shows the initial state before PWM starting with different polarity settings.
Содержание ISD94100 Series
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