ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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PWM Capture Interrupt Flag Register (PWM_CAPIF)
Register
Offset
R/W Description
Reset Value
PWM_CAPIF
0x254
R/W PWM Capture Interrupt Flag Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
CFLIF5
CFLIF4
CFLIF3
CFLIF2
CFLIF1
CFLIF0
7
6
5
4
3
2
1
0
Reserved
CRLIF5
CRLIF4
CRLIF3
CRLIF2
CRLIF1
CRLIF0
Bits
Description
[31:14]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[13]
CFLIF5
PWM Channel 5 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note:
When Capture with PDMA operating, CAPIF corresponding channel CFLIF will
cleared by hardware after PDMA transfer data.
[12]
CFLIF4
PWM Channel 4 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note:
When Capture with PDMA operating, CAPIF corresponding channel CFLIF will
cleared by hardware after PDMA transfer data.
[11]
CFLIF3
PWM Channel 3 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note:
When Capture with PDMA operating, CAPIF corresponding channel CFLIF will
cleared by hardware after PDMA transfer data.
[10]
CFLIF2
PWM Channel 2 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note:
When Capture with PDMA operating, CAPIF corresponding channel CFLIF will
cleared by hardware after PDMA transfer data.
[9]
CFLIF1
PWM Channel 1 Capture Falling Latch Interrupt Flag
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