ISD94100 Series Technical Reference Manual
Sep 9, 2019
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[25]
BRKLSTS1
PWM Channel 1 Level-detect Brake Status (Read Only)
0 = PWM channel 1 level-detect brake state is released.
1 = When PWM channel 1 level-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 1 at brake state.
Note:
This bit is read only and auto cleared by hardware. When enabled brake source return
to high level, PWM will release brake state until current PWM period finished. The PWM
waveform will start output from next full PWM period.
[24]
BRKLSTS0
PWM Channel 0 Level-detect Brake Status (Read Only)
0 = PWM channel 0 level-detect brake state is released.
1 = When PWM channel 0 level-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 0 at brake state.
Note:
This bit is read only and auto cleared by hardware. When enabled brake source return
to high level, PWM will release brake state until current PWM period finished. The PWM
waveform will start output from next full PWM period.
[23:22]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[21]
BRKESTS5
PWM Channel 5 Edge-detect Brake Status
0 = PWM channel 5 edge-detect brake state is released.
1 = When PWM channel 5 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 5 at brake state, writing 1 to clear.
[20]
BRKESTS4
PWM Channel 4 Edge-detect Brake Status
0 = PWM channel 4 edge-detect brake state is released.
1 = When PWM channel 4 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 4 at brake state, writing 1 to clear.
[19]
BRKESTS3
PWM Channel 3 Edge-detect Brake Status
0 = PWM channel 3 edge-detect brake state is released.
1 = When PWM channel 3 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 3 at brake state, writing 1 to clear.
[18]
BRKESTS2
PWM Channel 2 Edge-detect Brake Status
0 = PWM channel 2 edge-detect brake state is released.
1 = When PWM channel 2 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 2 at brake state, writing 1 to clear.
[17]
BRKESTS1
PWM Channel 1 Edge-detect Brake Status
0 = PWM channel 1 edge-detect brake state is released.
1 = When PWM channel 1 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 1 at brake state, writing 1 to clear.
[16]
BRKESTS0
PWM Channel 0 Edge-detect Brake Status
0 = PWM channel 0 edge-detect brake state is released.
1 = When PWM channel 0 edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel 0 at brake state, writing 1 to clear.
[15:14]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[13]
BRKLIF5
PWM Channel 5 Level-detect Brake Interrupt Flag (Write Protected)
0 = PWM channel 5 level-detect brake event do not happened.
1 = When PWM channel 5 level-detect brake event happened, this bit is set to 1, writing 1
to clear.
Note:
This register is write protected. Refer to SYS_REGLCTL register.
[12]
BRKLIF4
PWM Channel 4 Level-detect Brake Interrupt Flag (Write Protected)
Содержание ISD94100 Series
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