ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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APB Devices Clock Enable Control Register (CLK_APBCLK0)
The bits in this register are used to enable/disable clock for peripheral controller clocks.
Register
Offset
R/W Description
Reset Value
CLK_APBCLK0
0x08
R/W APB Devices Clock Enable Control Register 0
0x0000_0001
31
30
29
28
27
26
25
24
Reserved
I2S0CKEN
EADCCKEN
USBDCKEN
Reserved
23
22
21
20
19
18
17
16
Reserved
UART0CKEN
15
14
13
12
11
10
9
8
DMICCKEN
SPI2CKEN
SPI1CKEN
SPI0CKEN
Reserved
I2C1CKEN
I2C0CKEN
7
6
5
4
3
2
1
0
Reserved
CLKOCKEN
TMR3CKEN
TMR2CKEN
TMR1CKEN
TMR0CKEN
RTCCKEN
WDTCKEN
Bits
Description
[31:30]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[29]
I2S0CKEN
I
2
S0 Clock Enable Bit
0 = I
2
S0 Clock Disabled.
1 = I
2
S0 Clock Enabled.
[28]
EADCCKEN
Enhanced Analog-digital-converter (EADC) Clock Enable Bit
0 = EADC clock Disabled.
1 = EADC clock Enabled.
[27]
USBDCKEN
USB Device Clock Enable Bit
0 = USB Device clock Disabled.
1 = USB Device clock Enabled.
[26:17]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[16]
UART0CKEN
UART0 Clock Enable Bit
0 = UART0 clock Disabled.
1 = UART0 clock Enabled.
[15]
DMICCKEN
DMIC Clock Enable Bit
0 = DMIC clock Disabled.
1 = DMIC clock Enabled.
[14]
SPI2CKEN
SPI2 Clock Enable Bit
0 = SPI2 clock Disabled.
1 = SPI2 clock Enabled.
[13]
SPI1CKEN
SPI1 Clock Enable Bit
0 = SPI1 clock Disabled.
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