ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Banked Stack Pointer (SP)
Hardware integer divide instructions, SDIV and UDIV
Handler and Thread modes
Thumb and Debug states
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency
Automatic processor state saving and restoration for low latency
Interrupt Service
Routine (ISR)
entry and exit
Support for ARMv6 big-endian byte-invariant or little-endian accesses
Support for ARMv6 unaligned accesses
Floating Point Unit (FPU) in the Cortex
®
-M4F processor providing:
32-bit instructions for single-precision (C float) data-processing operations
Combined Multiply and Accumulate instructions for increased precision (Fused
MAC)
Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers
Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing. Features include:
External interrupts. Configurable from 1 to 240 (the ISD94100 series configured
with 97 interrupts)
Bits of priority, configurable from 3 to 8
Dynamic reprioritization of interrupts
Priority grouping which enables selection of preempting interrupt levels and non-
preempting interrupt levels
Support for tail-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration between
interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
Eight memory regions
Sub Region Disable (SRD), enabling efficient use of memory regions
The ability to enable a background region that implements the default memory
map attributes
Low-cost debug solution that features:
Debug access to all memory and registers in the system, including access to
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