ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
383
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Rev1.09
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ICA
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NCE
M
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U
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Timer PWM Counter Clock Source Register (TIMERx PWMCLKSRC)
Register
Offset
R/W Description
Reset Value
TIMER0_PWMCLKSRC
T0x44
R/W Timer0 PWM Counter Clock Source Register
0x0000_0000
TIMER1_PWMCLKSRC
T0x144
R/W Timer1 PWM Counter Clock Source Register
0x0000_0000
TIMER2_PWMCLKSRC
T0x44
R/W Timer2 PWM Counter Clock Source Register
0x0000_0000
TIMER3_PWMCLKSRC
T0x144
R/W Timer3 PWM Counter Clock Source Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CLKSRC
Bits
Description
[31:3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2:0]
CLKSRC
PWM Counter Clock Source Select
The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out
or capture event.
000 = TMRx_CLK.
001 = Internal TIMER0 time-out or capture event.
010 = Internal TIMER1 time-out or capture event.
011 = Internal TIMER2 time-out or capture event.
100 = Internal TIMER3 time-out or capture event.
Others = Reserved. Do not use.
Note:
If TIMER0 PWM function is enabled, the PWM counter clock source can be selected
from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt
events.
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